公开(公告)号：US07424660B2

公开(公告)日：2008-09-09

申请号：US11397822

申请日：2006-04-03

申请人： Omar Kebichi ,  Wu-Tung Cheng ,  Christopher John Hill ,  Paul J. Reuter ,  Yahya M. Z. Mustafa

发明人： Omar Kebichi ,  Wu-Tung Cheng ,  Christopher John Hill ,  Paul J. Reuter ,  Yahya M. Z. Mustafa

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G11C29/12015 ,  G11C29/14 ,  G11C29/56012 ,  G11C2029/0401 ,  G11C2029/2602

摘要： A circuit is disclosed for testing memories using multiple built-in self test (BIST) controllers embedded in an integrated circuit (IC). The BIST controllers are brought to a synchronization point during the memory test by allowing for a synchronization state. An output signal from an output pin on the IC indicates the existence of a synchronization state to automated test equipment (ATE). After an ATE receives the output signal, it issues a resume signal through an IC input pin that causes the controllers to advance out of the synchronization state. The ATE controls the synchronization state length by delaying the resume signal. Synchronization states can be used in parametric test algorithms, such as for retention and IDDQ tests. Synchronization states can be incorporated into user-defined algorithms by software design tools that generate an HDL description of a BIST controller operable to apply the algorithm with the synchronization state.

摘要翻译： 公开了一种用于使用嵌入在集成电路（IC）中的多个内置自测（BIST）控制器测试存储器的电路。 通过允许同步状态，BIST控制器在存储器测试期间被带到同步点。 来自IC上的输出引脚的输出信号表示存在与自动测试设备（ATE）的同步状态。 ATE接收到输出信号后，通过IC输入引脚发出一个恢复信号，导致控制器进入同步状态。 ATE通过延迟恢复信号来控制同步状态长度。 同步状态可用于参数化测试算法，例如保留和IDDQ测试。 可以通过软件设计工具将同步状态并入用户定义的算法，该工具可生成可操作以将同步状态应用于算法的BIST控制器的HDL描述。

公开(公告)号：US07036064B1

公开(公告)日：2006-04-25

申请号：US09872212

申请日：2001-05-31

申请人： Omar Kebichi ,  Wu-Tung Cheng ,  Christopher John Hill ,  Paul J. Reuter ,  Yahya M. Z. Mustafa

发明人： Omar Kebichi ,  Wu-Tung Cheng ,  Christopher John Hill ,  Paul J. Reuter ,  Yahya M. Z. Mustafa

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G11C29/12015 ,  G11C29/14 ,  G11C29/56012 ,  G11C2029/0401 ,  G11C2029/2602

摘要： A circuit is disclosed for testing memories using multiple built-in self test (BIST) controllers embedded in an integrated circuit (IC). The BIST controllers are brought to a synchronization point during the memory test by allowing for a synchronization state. An output signal from an output pin on the IC indicates the existence of a synchronization state to automated test equipment (ATE). After an ATE receives the output signal, it issues a resume signal through an IC input pin that causes the controllers to advance out of the synchronization state. The ATE controls the synchronization state length by delaying the resume signal. Synchronization states can be used in parametric test algorithms, such as for retention and IDDQ tests. Synchronization states can be incorporated into user-defined algorithms by software design tools that generate an HDL description of a BIST controller operable to apply the algorithm with the synchronization state.

公开(公告)号：US06934897B2

公开(公告)日：2005-08-23

申请号：US10210794

申请日：2002-07-31

申请人： Nilanjan Mukherjee ,  Chien-Chung Tsai ,  Wu-Tung Cheng ,  Omer Ghazi Samman ,  Yahya M. Z. Mustafa ,  Paul J. Reuter ,  Yu Huang ,  Sudhakar Mannapuram Reddy

发明人： Nilanjan Mukherjee ,  Chien-Chung Tsai ,  Wu-Tung Cheng ,  Omer Ghazi Samman ,  Yahya M. Z. Mustafa ,  Paul J. Reuter ,  Yu Huang ,  Sudhakar Mannapuram Reddy

IPC分类号： G01R31/3193 ,  G01R31/28

CPC分类号： G01R31/3193

摘要： Methods are described for scheduling the concurrent testing of multiple cores embedded in an integrated circuit. Test scheduling is performed by formulating the problem as a bin-packing problem and using a modified two-dimensional or three-dimensional bin-packing heuristic. The tests of multiple cores are represented as functions of at least the integrated circuit pins used to test the core and the core test time. The representations may include a third dimension of peak power required to test the core. The test schedule is represented as a bin having dimensions of at least integrated circuit pins and integrated circuit test time. The bin may include a third dimension of peak power. The scheduling of the multiple cores is accomplished by fitting the multiple core test representations into the bin.

摘要翻译： 描述了用于调度嵌入在集成电路中的多个核的并发测试的方法。 通过将问题解决为二进制包装问题并使用修改后的二维或三维二进制包装启发式来进行测试调度。 多个核心的测试表示为至少用于测试核心和核心测试时间的集成电路引脚的功能。 表示可以包括测试核心所需的峰值功率的第三维度。 测试计划表示为具有至少集成电路引脚和集成电路测试时间的尺寸的存储区。 箱可以包括峰值功率的第三维度。 多核的调度是通过将多个核心测试表示拟合到bin来实现的。

公开(公告)号：US06671843B1

公开(公告)日：2003-12-30

申请号：US09737620

申请日：2000-12-14

申请人： Omar Kebichi ,  Christopher John Hill ,  Paul J. Reuter ,  Ian Alexander Burgess

发明人： Omar Kebichi ,  Christopher John Hill ,  Paul J. Reuter ,  Ian Alexander Burgess

IPC分类号： G01R3128

CPC分类号： G11C29/10 ,  G11C29/16 ,  G11C29/50

摘要： A method performed by a software design tool for providing an algorithm to a BIST controller that tests memory within a circuit. The method includes reading a description of a user defined test algorithm for a BIST controller, translating the description into an in-memory representation of the user defined algorithm, and reading a memory model selected by a user. The in-memory representation of the user-defined algorithm is associated with the selected memory model. From the association an HDL description of a BIST controller is generated. The HDL description is operable to apply the user defined algorithm to a memory corresponding to the selected memory model.

摘要翻译： 由软件设计工具执行的方法，用于向BIST控制器提供测试电路内的存储器的算法。 该方法包括读取用于BIST控制器的用户定义的测试算法的描述，将描述转换成用户定义算法的存储器内表示，以及读取由用户选择的存储器模型。 用户定义的算法的内存中的表示与所选择的存储器模型相关联。 从关联中生成BIST控制器的HDL描述。 HDL描述可操作以将用户定义的算法应用于对应于所选存储器模型的存储器。

公开(公告)号：US06456961B1

公开(公告)日：2002-09-24

申请号：US09302699

申请日：1999-04-30

申请人： Srinivas Patil ,  Wu-Tung Cheng ,  Paul J. Reuter

发明人： Srinivas Patil ,  Wu-Tung Cheng ,  Paul J. Reuter

IPC分类号： G06F1750

CPC分类号： G01R31/318505

摘要： A computer-implemented method and apparatus for creating a testable circuit design that includes one or more embedded cores. The method includes identifying an embedded core within the circuit design; associating certain pins of the embedded core with pins of the circuit design; and inserting into the circuit design access circuitry coupling the certain connection pins of the embedded core to the associated pins of the circuit design. The method further includes providing test vectors for the embedded core; and generating test vectors for the circuit design by mapping the core test vectors applicable to the certain pins of the embedded core to the associated pins of the circuit design. The cores within the circuit design can then be tested after manufacture by applying the design test vectors to the circuit design.

摘要翻译： 一种用于创建包括一个或多个嵌入式核心的可测试电路设计的计算机实现的方法和装置。 该方法包括识别电路设计内的嵌入式核心; 将嵌入式核心的某些引脚与电路设计的引脚相关联; 并将插入到嵌入式芯的某些连接引脚的电路设计访问电路插入电路设计的相关引脚。 该方法还包括提供用于嵌入式核心的测试向量; 以及通过将适用于嵌入式核心的某些引脚的核心测试向量映射到电路设计的相关引脚来生成用于电路设计的测试向量。 然后可以通过将设计测试矢量应用于电路设计，然后在制造后对电路设计中的核心进行测试。