公开(公告)号：US20170338941A1

公开(公告)日：2017-11-23

申请号：US15159583

申请日：2016-05-19

申请人： OmniVision Technologies, Inc.

发明人： Li YANG ,  Wengen WANG ,  Charles Qingle WU

IPC分类号： H04L7/033 ,  H04L5/00 ,  H04B1/69

CPC分类号： H04L7/0331 ,  G06F1/08 ,  H03K3/84 ,  H03K5/00 ,  H03K5/1252 ,  H03K5/131 ,  H03K5/133 ,  H03K5/14 ,  H03L7/16 ,  H04B1/69 ,  H04B15/02 ,  H04L5/005

摘要： A spread-spectrum clock generator has a phase-locked loop locked to a reference signal that gives a stable-frequency output to a variable phase shifter. The variable phase shifter provides a spread-spectrum clock output because its phase-shift is determined by a pseudorandom sequence generator and the pseudorandom sequence generator changes its output regularly or irregularly within limits. The clock generator performs a method of generating a spread-spectrum clock including locking the phase-locked loop to the reference signal, and phase shifting the stable frequency signal by a phase-shift determined by the pseudorandom sequence generator; and changing the phase-shift determined by the pseudorandom sequence generator. Since phase shifting is performed open-loop, total phase shift is defined by design.

公开(公告)号：US20180152177A1

公开(公告)日：2018-05-31

申请号：US15365605

申请日：2016-11-30

申请人： OmniVision Technologies, Inc.

发明人： Li YANG ,  Charles Qingle WU

IPC分类号： H03K3/0231 ,  H03B5/24 ,  H03K4/50

CPC分类号： H03K3/0231 ,  H03B5/24 ,  H03K3/011 ,  H03K3/354 ,  H03K4/50

摘要： An integrated oscillator has an R-S flipflop; a first and second capacitor; a current source transistor; first and second current-steering transistors, each having a source coupled to the current source transistor, with drains coupled to the first and second capacitor respectively. The first current-steering transistor has gate coupled to a first output of the R-S flipflop, and the second current-steering transistor has gate coupled to a second output of the R-S flipflop. The oscillator has a first sense inverter having input from the first capacitor and powered by a feedback circuit adapted to sense voltages on the first and second capacitor; and a second sense inverter having input from the second capacitor and powered by the feedback circuit. The R-S flipflop has a first input coupled to an output of the first sense inverter and a second input coupled to an output of the second sense inverter.

公开(公告)号：US20170373825A1

公开(公告)日：2017-12-28

申请号：US15673298

申请日：2017-08-09

申请人： OmniVision Technologies, Inc.

发明人： Charles Qingle WU ,  Qi NIU

IPC分类号： H04L7/033 ,  H03L7/085 ,  G06F7/68 ,  G06F1/08 ,  G11B20/14 ,  H03L7/099 ,  H03C3/09

CPC分类号： H04L7/0331 ,  G06F1/08 ,  G06F7/68 ,  G11B20/1423 ,  H03C3/0925 ,  H03C3/0933 ,  H03L7/085 ,  H03L7/0991 ,  H03L7/18

摘要： A frequency divider unit has a digital frequency divider configured to divide by an odd integer, and a dual-edge-triggered one-shot coupled to double frequency of an output of the digital frequency divider. The frequency divider unit is configurable to divide an input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, and 3.5. In embodiments, the frequency divider unit relies on circuit delays to determine an output pulsewidth, and in other embodiments the output pulsewidth is determined from a clock signal. In embodiments, the unit is configurable to divide an input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, 3.5, 4.5, 5.5, 6.5, and 7.5 as well as many integer ratios including 2, 4, 6, and 8. In embodiments, the digital frequency divider is configurable to provide a 50% duty cycle to the one-shot.