公开(公告)号：US07846828B2

公开(公告)日：2010-12-07

申请号：US12338395

申请日：2008-12-18

申请人： Osamu Kusumoto ,  Makoto Kitabatake ,  Masao Uchida ,  Kunimasa Takahashi ,  Kenya Yamashita ,  Masahiro Hagio ,  Kazuyuki Sawada

发明人： Osamu Kusumoto ,  Makoto Kitabatake ,  Masao Uchida ,  Kunimasa Takahashi ,  Kenya Yamashita ,  Masahiro Hagio ,  Kazuyuki Sawada

IPC分类号： H01L21/28 ,  H01L21/44

CPC分类号： H01L29/7828 ,  H01L21/046 ,  H01L21/0475 ,  H01L21/0485 ,  H01L21/30625 ,  H01L29/1029 ,  H01L29/105 ,  H01L29/1608 ,  H01L29/365 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/7838 ,  H01L29/812

摘要： Ion implantation is carried out to form a p-well region and a source region in parts of a high resistance SiC layer on a SiC substrate, and a carbon film is deposited over the substrate. With the carbon film deposited over the substrate, annealing for activating the implanted dopant ions is performed, and then the carbon film is removed. Thus, a smooth surface having hardly any surface roughness caused by the annealing is obtained. Furthermore, if a channel layer is epitaxially grown, the surface roughness of the channel layer is smaller than that of the underlying layer. Since the channel layer having a smooth surface is provided, it is possible to obtain a MISFET with a high current drive capability.

摘要翻译： 进行离子注入以在SiC衬底上的高电阻SiC层的部分中形成p阱区域和源极区域，并且在衬底上沉积碳膜。 通过沉积在基板上的碳膜，进行用于激活注入的掺杂离子的退火，然后除去碳膜。 因此，获得了退火几乎没有表面粗糙度的光滑表面。 此外，如果沟道层外延生长，则沟道层的表面粗糙度小于下层的表面粗糙度。 由于提供了具有平滑表面的沟道层，所以可以获得具有高电流驱动能力的MISFET。

公开(公告)号：US07473929B2

公开(公告)日：2009-01-06

申请号：US10880550

申请日：2004-07-01

申请人： Osamu Kusumoto ,  Makoto Kitabatake ,  Masao Uchida ,  Kunimasa Takahashi ,  Kenya Yamashita ,  Masahiro Hagio ,  Kazuyuki Sawada

发明人： Osamu Kusumoto ,  Makoto Kitabatake ,  Masao Uchida ,  Kunimasa Takahashi ,  Kenya Yamashita ,  Masahiro Hagio ,  Kazuyuki Sawada

IPC分类号： H01L29/15 ,  H01L31/0312

CPC分类号： H01L29/7828 ,  H01L21/046 ,  H01L21/0475 ,  H01L21/0485 ,  H01L21/30625 ,  H01L29/1029 ,  H01L29/105 ,  H01L29/1608 ,  H01L29/365 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/7838 ,  H01L29/812

摘要： Ion implantation is carried out to form a p-well region and a source region in parts of a high resistance SiC layer on a SiC substrate, and a carbon film is deposited over the substrate. With the carbon film deposited over the substrate, annealing for activating the implanted dopant ions is performed, and then the carbon film is removed. Thus, a smooth surface having hardly any surface roughness caused by the annealing is obtained. Furthermore, if a channel layer is epitaxially grown, the surface roughness of the channel layer is smaller than that of the underlying layer. Since the channel layer having a smooth surface is provided, it is possible to obtain a MISFET with a high current drive capability.

摘要翻译： 进行离子注入以在SiC衬底上的高电阻SiC层的部分中形成p阱区域和源极区域，并且在衬底上沉积碳膜。 通过沉积在基板上的碳膜，进行用于激活注入的掺杂离子的退火，然后除去碳膜。 因此，获得了退火几乎没有表面粗糙度的光滑表面。 此外，如果沟道层外延生长，则沟道层的表面粗糙度小于下层的表面粗糙度。 由于提供了具有平滑表面的沟道层，所以可以获得具有高电流驱动能力的MISFET。

公开(公告)号：US20050001217A1

公开(公告)日：2005-01-06

申请号：US10880550

申请日：2004-07-01

申请人： Osamu Kusumoto ,  Makoto Kitabatake ,  Masao Uchida ,  Kunimasa Takahashi ,  Kenya Yamashita ,  Masahiro Hagio ,  Kazuyuki Sawada

发明人： Osamu Kusumoto ,  Makoto Kitabatake ,  Masao Uchida ,  Kunimasa Takahashi ,  Kenya Yamashita ,  Masahiro Hagio ,  Kazuyuki Sawada

IPC分类号： H01L21/04 ,  H01L29/10 ,  H01L29/15 ,  H01L29/24 ,  H01L29/36 ,  H01L29/78 ,  H01L29/812 ,  G03F9/00

CPC分类号： H01L29/7828 ,  H01L21/046 ,  H01L21/0475 ,  H01L21/0485 ,  H01L21/30625 ,  H01L29/1029 ,  H01L29/105 ,  H01L29/1608 ,  H01L29/365 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/7838 ,  H01L29/812

摘要： Ion implantation is carried out to form a p-well region and a source region in parts of a high resistance SiC layer on a SiC substrate, and a carbon film is deposited over the substrate. With the carbon film deposited over the substrate, annealing for activating the implanted dopant ions is performed, and then the carbon film is removed. Thus, a smooth surface having hardly any surface roughness caused by the annealing is obtained. Furthermore, if a channel layer is epitaxially grown, the surface roughness of the channel layer is smaller than that of the underlying layer. Since the channel layer having a smooth surface is provided, it is possible to obtain a MISFET with a high current drive capability.

摘要翻译： 进行离子注入以在SiC衬底上的高电阻SiC层的部分中形成p阱区域和源极区域，并且在衬底上沉积碳膜。 通过沉积在基板上的碳膜，进行用于激活注入的掺杂离子的退火，然后除去碳膜。 因此，获得了退火几乎没有表面粗糙度的光滑表面。 此外，如果沟道层外延生长，则沟道层的表面粗糙度小于下层的表面粗糙度。 由于提供了具有平滑表面的沟道层，所以可以获得具有高电流驱动能力的MISFET。

公开(公告)号：US09018699B2

公开(公告)日：2015-04-28

申请号：US13814433

申请日：2012-09-12

申请人： Tsutomu Kiyosawa ,  Kazuyuki Sawada ,  Kunimasa Takahashi ,  Yuki Tomita

发明人： Tsutomu Kiyosawa ,  Kazuyuki Sawada ,  Kunimasa Takahashi ,  Yuki Tomita

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L29/16 ,  H01L21/04 ,  H01L29/78 ,  H01L29/812 ,  H01L29/872

CPC分类号： H01L21/02378 ,  H01L21/0475 ,  H01L21/049 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7827 ,  H01L29/8128 ,  H01L29/872

摘要： A SiC semiconductor element includes: a SiC substrate which has a principal surface tilted with respect to a (0001) Si plane; a SiC layer arranged on the principal surface of the substrate; a trench arranged in the SiC layer and having a bottom, a sidewall, and an upper corner region located between the sidewall and the upper surface of the SiC layer; a gate insulating film arranged on at least a part of the sidewall and on at least a part of the upper corner region of the trench and on at least a part of the upper surface of the SiC layer; and a gate electrode arranged on the gate insulating film. The upper corner region has a different surface from the upper surface of the SiC layer and from a surface that defines the sidewall. The gate electrode contacts with both of a first portion of the gate insulating film located on the upper corner region and a second portion of the gate insulating film located on the sidewall. The first portion of the gate insulating film is thicker than a third portion of the gate insulating film located on the upper surface of the SiC layer. And an end portion of the gate electrode is located on the upper corner region.

摘要翻译： SiC半导体元件包括：具有相对于（0001）Si平面倾斜的主表面的SiC衬底; 设置在所述基板的主表面上的SiC层; 布置在所述SiC层中并且具有位于所述SiC层的侧壁和所述上表面之间的底部，侧壁和上角区域的沟槽; 栅极绝缘膜，布置在所述沟槽的所述侧壁的至少一部分和所述上部拐角区域的至少一部分上以及所述SiC层的上表面的至少一部分上; 以及设置在栅极绝缘膜上的栅电极。 上角区域具有与SiC层的上表面和限定侧壁的表面不同的表面。 栅电极与位于上角区域的栅极绝缘膜的第一部分和位于侧壁上的栅极绝缘膜的第二部分接触。 栅极绝缘膜的第一部分比位于SiC层的上表面上的栅极绝缘膜的第三部分厚。 并且栅电极的端部位于上角区域。

公开(公告)号：US20130168701A1

公开(公告)日：2013-07-04

申请号：US13814433

申请日：2012-09-12

申请人： Tsutomu Kiyosawa ,  Kazuyuki Sawada ,  Kunimasa Takahashi ,  Yuki Tomita

发明人： Tsutomu Kiyosawa ,  Kazuyuki Sawada ,  Kunimasa Takahashi ,  Yuki Tomita

IPC分类号： H01L21/02 ,  H01L29/16

CPC分类号： H01L21/02378 ,  H01L21/0475 ,  H01L21/049 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7827 ,  H01L29/8128 ,  H01L29/872

摘要： A SiC semiconductor element includes: a SiC substrate which has a principal surface tilted with respect to a (0001) Si plane; a SiC layer arranged on the principal surface of the substrate; a trench arranged in the SiC layer and having a bottom, a sidewall, and an upper corner region located between the sidewall and the upper surface of the SiC layer; a gate insulating film arranged on at least a part of the sidewall and on at least a part of the upper corner region of the trench and on at least a part of the upper surface of the SiC layer; and a gate electrode arranged on the gate insulating film. The upper corner region has a different surface from the upper surface of the SiC layer and from a surface that defines the sidewall. The gate electrode contacts with both of a first portion of the gate insulating film located on the upper corner region and a second portion of the gate insulating film located on the sidewall. The first portion of the gate insulating film is thicker than a third portion of the gate insulating film located on the upper surface of the SiC layer. And an end portion of the gate electrode is located on the upper corner region.

摘要翻译： SiC半导体元件包括：具有相对于（0001）Si平面倾斜的主表面的SiC衬底; 设置在所述基板的主表面上的SiC层; 布置在所述SiC层中并且具有位于所述SiC层的侧壁和所述上表面之间的底部，侧壁和上角区域的沟槽; 栅极绝缘膜，布置在所述沟槽的所述侧壁的至少一部分和所述上部拐角区域的至少一部分上以及所述SiC层的上表面的至少一部分上; 以及设置在栅极绝缘膜上的栅电极。 上角区域具有与SiC层的上表面和限定侧壁的表面不同的表面。 栅电极与位于上角区域的栅极绝缘膜的第一部分和位于侧壁上的栅极绝缘膜的第二部分接触。 栅极绝缘膜的第一部分比位于SiC层的上表面上的栅极绝缘膜的第三部分厚。 并且栅电极的端部位于上角区域。

公开(公告)号：US20060055064A1

公开(公告)日：2006-03-16

申请号：US11204052

申请日：2005-08-16

申请人： Saichirou Kaneko ,  Kazuyuki Sawada ,  Toshihiko Uno

发明人： Saichirou Kaneko ,  Kazuyuki Sawada ,  Toshihiko Uno

IPC分类号： H01L23/28

CPC分类号： H01L23/3135 ,  H01L23/3192 ,  H01L2224/48465 ,  H01L2924/13091 ,  H01L2924/3025

摘要： An ion-through region 100, 102 is provided as a first opening in a passivation film 90 on a source electrode 70 and a drain electrode 80. The passivation film 90 is coated with a sealing resin to package the semiconductor device. At this point, the ion-through region 100, 102 is filled with the sealing resin to put the sealing resin into direct contact with the source electrode 70 and the drain electrode 80. With this structure, movable ions accumulated at an interface of the sealing resin with the passivation film 90 in a high temperature and high humidity atmosphere are discharged to the source electrode 70 and the drain electrode 80 via the ion-through region 100, 102 and thus do not influence an N−-type extended drain region 30. Therefore, the drain breakdown voltage can be improved.

摘要翻译： 在源电极70和漏极电极80上的钝化膜90中设置有离子通过区域100,102作为第一开口。钝化膜90涂覆有密封树脂以封装半导体器件。 此时，通过密封树脂填充离子通过区域100,102，使密封树脂与源极电极70和漏极电极80直接接触。利用该结构，可动离子积聚在密封件 具有钝化膜90的高温高湿气氛中的树脂通过离子通过区域100,102而被排出到源电极70和漏电极80，因此不会影响N + 型扩展漏区30.因此，可以提高漏极击穿电压。

公开(公告)号：US07301179B2

公开(公告)日：2007-11-27

申请号：US11204052

申请日：2005-08-16

申请人： Saichirou Kaneko ,  Kazuyuki Sawada ,  Toshihiko Uno

发明人： Saichirou Kaneko ,  Kazuyuki Sawada ,  Toshihiko Uno

IPC分类号： H01L29/66

CPC分类号： H01L23/3135 ,  H01L23/3192 ,  H01L2224/48465 ,  H01L2924/13091 ,  H01L2924/3025

摘要： An ion-through region 100, 102 is provided as a first opening in a passivation film 90 on a source electrode 70 and a drain electrode 80. The passivation film 90 is coated with a sealing resin to package the semiconductor device. At this point, the ion-through region 100, 102 is filled with the sealing resin to put the sealing resin into direct contact with the source electrode 70 and the drain electrode 80. With this structure, movable ions accumulated at an interface of the sealing resin with the passivation film 90 in a high temperature and high humidity atmosphere are discharged to the source electrode 70 and the drain electrode 80 via the ion-through region 100, 102 and thus do not influence an N−-type extended drain region 30. Therefore, the drain breakdown voltage can be improved.

摘要翻译： 在源电极70和漏电极80上的钝化膜90中设置有离子通过区域100,102作为第一开口。 钝化膜90涂覆有密封树脂以封装半导体器件。 此时，通过密封树脂填充离子通过区域100,102，使密封树脂与源电极70和漏电极80直接接触。 利用这种结构，在高温和高湿度气氛下积聚在密封树脂与钝化膜90的界面处的可移动离子通过离子通过区域100,102被排放到源电极70和漏电极80，因此 不影响N + - 型扩展漏极区域30。 因此，可以提高漏极击穿电压。

公开(公告)号：US06835270B2

公开(公告)日：2004-12-28

申请号：US10158158

申请日：2002-05-31

申请人： Tetsuo Imada ,  Shigeru Namiki ,  Kazuyuki Sawada ,  Toshiyuki Fujioka ,  Takaaki Higashida ,  Mamoru Inoue

发明人： Tetsuo Imada ,  Shigeru Namiki ,  Kazuyuki Sawada ,  Toshiyuki Fujioka ,  Takaaki Higashida ,  Mamoru Inoue

IPC分类号： B29D1700

CPC分类号： B29C65/521 ,  B29C65/1406 ,  B29C65/1435 ,  B29C65/1483 ,  B29C65/4845 ,  B29C65/528 ,  B29C66/1122 ,  B29C66/452 ,  B29C66/71 ,  B29C66/9532 ,  B29C66/9534 ,  B29D17/005 ,  B29L2017/005 ,  G11B7/26 ,  B29K2069/00

摘要： There is provided a process of producing a laminate type optical disk comprising the steps of: (1) molding a pair of substrates of a transparent resin at least one of which substrates has irregularities on its one main surface; (2) forming a metal thin film on said one main surface having the irregularities, and then (3) laminating the pair of the substrates while the metal thin film is located inside and bonding the substrates by means of an adhesive which is supplied between the substrates, the process being characterized in that after the step (1), a waiting treatment is carried out in which the molded substrates are cooled to such a temperature that a difference between said temperature and a temperature of an atmosphere surrounding the substrates is not greater than 5° C. while keeping a moisture (or water) content of the substrates not larger than 0.1% by weight, and then the step (2) is carried out.

摘要翻译： 提供了一种制造层压型光盘的方法，包括以下步骤：（1）在其一个主表面上成型一对基板，其中至少一个基板具有不规则性;（2）形成金属薄片 在所述一个主表面上具有不规则性的膜，然后（3）在金属薄膜位于内部并且通过提供在基板之间的粘合剂粘合基板的同时层压一对基板，该工艺的特征在于 在步骤（1）之后，进行等待处理，其中将成型基板冷却至使温度与基板周围的气氛的温度之间的差不大于5℃的温度，同时保持 基材的水分（或水）含量不大于0.1重量％，然后进行步骤（2）。

公开(公告)号：US06416609B1

公开(公告)日：2002-07-09

申请号：US09368424

申请日：1999-08-05

申请人： Tetsuo Imada ,  Shigeru Namiki ,  Kazuyuki Sawada ,  Toshiyuki Fujioka ,  Takaaki Higashida ,  Mamoru Inoue

发明人： Tetsuo Imada ,  Shigeru Namiki ,  Kazuyuki Sawada ,  Toshiyuki Fujioka ,  Takaaki Higashida ,  Mamoru Inoue

IPC分类号： B29D1700

CPC分类号： B29C65/521 ,  B29C65/1406 ,  B29C65/1435 ,  B29C65/1483 ,  B29C65/4845 ,  B29C65/528 ,  B29C66/1122 ,  B29C66/452 ,  B29C66/71 ,  B29C66/9532 ,  B29C66/9534 ,  B29D17/005 ,  B29L2017/005 ,  G11B7/26 ,  B29K2069/00

摘要： There is provided a process of producing a laminate type optical disk comprising the steps of: (1) molding a pair of substrates of a transparent resin at least one of which substrates has irregularities on its one main surface; (2) forming a metal thin film on said one main surface having the irregularities, and then (3) laminating the pair of the substrates while the metal thin film is located inside and bonding the substrates by means of an adhesive which is supplied between the substrates, the process being characterized in that after the step (1), a waiting treatment is carried out in which the molded substrates are cooled to such a temperature that a difference between said temperature and a temperature of an atmosphere surrounding the substrates is not greater than 5° C. while keeping a moisture (or water) content of the substrates not larger than 0.1% by weight, and then the step (2) is carried out.

摘要翻译： 提供了一种制造层压型光盘的方法，包括以下步骤：（1）在其一个主表面上模制一对基板，其中至少一个基板具有不规则性;（2）形成金属薄层 在所述一个主表面上具有不规则性的膜，然后（3）在金属薄膜位于内部并且通过提供在基板之间的粘合剂粘合基板的同时层压一对基板，该工艺的特征在于 在步骤（1）之后，进行等待处理，其中将成型基板冷却至使温度与基板周围的气氛的温度之间的差不大于5℃的温度，同时保持 基材的水分（或水）含量不大于0.1重量％，然后进行步骤（2）。

公开(公告)号：US5989998A

公开(公告)日：1999-11-23

申请号：US919271

申请日：1997-08-28

申请人： Gaku Sugahara ,  Nobuo Aoi ,  Koji Arai ,  Kazuyuki Sawada

发明人： Gaku Sugahara ,  Nobuo Aoi ,  Koji Arai ,  Kazuyuki Sawada

IPC分类号： C23C16/26 ,  C23C16/30 ,  C23C16/40 ,  H01L21/3105 ,  H01L21/312 ,  H01L21/314 ,  H01L21/316 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/02126 ,  C23C16/26 ,  C23C16/30 ,  C23C16/401 ,  H01L21/0212 ,  H01L21/02131 ,  H01L21/02205 ,  H01L21/02211 ,  H01L21/02214 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/3122 ,  H01L21/3127 ,  H01L21/314 ,  H01L21/31608 ,  H01L21/31612 ,  H01L21/31629 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/31051 ,  H01L21/31058

摘要： A material containing, as a main component, an organic silicon compound represented by the following general formula:R.sup.1.sub.x Si(OR.sup.2).sub.4-x(where R.sup.1 is a phenyl group or a vinyl group; R.sup.2 is an alkyl group; and x is an integer of 1 to 3) is caused to undergo plasma polymerization or react with an oxidizing agent to form an interlayer insulating film composed of a silicon oxide film containing an organic component. As the organic silicon compound where R.sup.1 is a phenyl group, there can be listed phenyltrimethoxysilane or diphenyldimethoxysilane. As the organic silicon compound where R.sup.1 is a vinyl group, there can be listed vinyltrimethoxysilane or divinyldimethoxysilane.

摘要翻译： 作为主成分的含有以下通式表示的有机硅化合物的材料：R1xSi（OR2）4-x（其中R1为苯基或乙烯基; R2为烷基; x为整数） 1〜3）进行等离子体聚合或与氧化剂反应，形成由含有有机成分的氧化硅膜构成的层间绝缘膜。 作为R 1为苯基的有机硅化合物，可以列举苯基三甲氧基硅烷或二苯基二甲氧基硅烷。 作为R 1为乙烯基的有机硅化合物，可列举乙烯基三甲氧基硅烷或二乙烯基二甲氧基硅烷。