公开(公告)号：US10193569B2

公开(公告)日：2019-01-29

申请号：US14477867

申请日：2014-09-05

申请人： PHISON ELECTRONICS CORP.

发明人： Chien-Fu Tseng ,  Tsai-Cheng Lin ,  Yen-Chiao Lai

IPC分类号： H03M13/11 ,  H04L1/00 ,  H03M13/25 ,  G06F11/07 ,  H03M13/37 ,  H03M13/29

摘要： A decoding method, a memory storage device and a memory control circuit unit are provided. The decoding method includes: executing at least one first iteration decoding procedure of an LDPC on a first codeword according to a first clock signal by a correcting circuit; generating a control parameter according to a first iteration count of the first iteration decoding procedure; outputting a second clock signal to the correcting circuit according to the control parameter; and executing at least one second iteration decoding procedure of the LDPC on a second codeword according to the second clock signal by the correcting circuit.

公开(公告)号：US20160020784A1

公开(公告)日：2016-01-21

申请号：US14477867

申请日：2014-09-05

申请人： PHISON ELECTRONICS CORP.

发明人： Chien-Fu Tseng ,  Tsai-Cheng Lin ,  Yen-Chiao Lai

IPC分类号： H03M13/11

CPC分类号： H03M13/1128 ,  G06F11/076 ,  H03M13/255 ,  H03M13/2948 ,  H03M13/3707 ,  H03M13/3746 ,  H03M13/3753 ,  H04L1/005

摘要： A decoding method, a memory storage device and a memory control circuit unit are provided. The decoding method includes: executing at least one first iteration decoding procedure of an LDPC on a first codeword according to a first clock signal by a correcting circuit; generating a control parameter according to a first iteration count of the first iteration decoding procedure; outputting a second clock signal to the correcting circuit according to the control parameter; and executing at least one second iteration decoding procedure of the LDPC on a second codeword according to the second clock signal by the correcting circuit.

摘要翻译： 提供了解码方法，存储器存储装置和存储器控制电路单元。 解码方法包括：通过校正电路根据第一时钟信号在第一码字上执行LDPC的至少一个第一迭代解码过程; 根据所述第一迭代解码过程的第一迭代次数生成控制参数; 根据所述控制参数向所述校正电路输出第二时钟信号; 以及通过所述校正电路根据所述第二时钟信号在第二码字上执行所述LDPC的至少一个第二迭代解码过程。