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1.发明授权System and method for avoiding error mechanisms in layered iterative decoding 有权用于避免分层迭代解码中的错误机制的系统和方法公开(公告)号：US08984376B1
公开(公告)日：2015-03-17
申请号：US13860411
申请日：2013-04-10
申请人： PMC-Sierra US, Inc.
CPC分类号： H03M13/1142 , H03M13/1114 , H03M13/1117 , H03M13/114
摘要： A low-density parity check (LDPC) decoder is provided for decoding low-density parity check (LDPC) encoded data wherein the processing order of the layers of the LDPC parity check matrix are rearranged during the decode process in an attempt to avoid error mechanisms brought about by the iterative nature of the LDPC belief propagation decoding process, such as stopping sets and trapping sets.
摘要翻译： 提供了一种用于解码低密度奇偶校验（LDPC）编码数据的低密度奇偶校验（LDPC）解码器，其中LDPC解码校验矩阵的层的处理顺序在解码过程期间被重新排列，以试图避免错误机制 由LDPC置信传播解码处理的迭代性质，如停止集合和陷阱集合引起的。
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公开(公告)号：US08984365B1
公开(公告)日：2015-03-17
申请号：US13860300
申请日：2013-04-10
申请人： PMC-Sierra US, Inc.
CPC分类号： H03M13/1111 , H03M13/1117 , H03M13/1122
摘要： A low-density parity check (LDPC) decoder is provided that eliminates the need to calculate customized check node codeword estimates by considering the check node processor and the variable node processor as a single processer having a shared memory for storing common variables to be used during both the check node processing and the variable node processing of the iterative decoding method.
摘要翻译： 提供了一种低密度奇偶校验（LDPC）解码器，其消除了通过考虑校验节点处理器和可变节点处理器作为具有共享存储器的单个处理器来计算定制校验节点代码字估计的需要，用于存储要在 校验节点处理和可变节点处理的迭代解码方法。
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3.发明申请公开(公告)号：US20140281828A1
公开(公告)日：2014-09-18
申请号：US14210971
申请日：2014-03-14
申请人： PMC-SIERRA US, INC.
发明人： Rino Micheloni , Alessia Marelli , Peter Z. Onufryk , Christopher I. W. Norrie , Ihab Jaser , Luca Crippa
IPC分类号： H03M13/11
CPC分类号： G06F11/00 , G06F11/1048 , H03M13/1111 , H03M13/3769
摘要： A system and method reading, accumulating and processing soft information for use in LDPC decoding. In accordance with the present invention, an LDPC decoder includes accumulation circuitry to receive soft reads of a cell of the nonvolatile memory storage module and to produce an accumulated soft read that can be used to identify an appropriate LLR for the cell. The accumulation circuitry of the present invention may include, an accumulation RAM, an arithmetic logic unit (ALU) and a soft accumulation control and sequencing module for accumulating and processing soft information for use in LDPC decoding.
摘要翻译： 读取，累加和处理用于LDPC解码的软信息的系统和方法。 根据本发明，LDPC解码器包括用于接收非易失性存储器存储模块的单元的软读取的积累电路，并且产生可用于识别该单元的适当LLR的累积软读。 本发明的累积电路可以包括累加RAM，算术逻辑单元（ALU）和用于累积和处理用于LDPC解码的软信息的软累积控制和排序模块。
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公开(公告)号：US08990661B1
公开(公告)日：2015-03-24
申请号：US13785848
申请日：2013-03-05
申请人： PMC-Sierra US, Inc.
CPC分类号： H03M13/114 , G06F11/1048 , H03M13/112
摘要： A low-density parity check (LDPC) decoder is provided for decoding low-density parity check (LDPC) encoded data wherein a layer specific attenuation factor is provided for each layer of the LDPC parity check matrix. An attenuation factor matrix comprising a plurality of coefficients specifies the specific attenuation factor for each layer and each iteration of the decoding process. A check node processor performs check node processing for each layer of the parity check matrix associated with the LDPC encoded codeword utilizing the normalized layered min-sum algorithm wherein the attenuation factor of the min-sum algorithm is determined by the coefficients of the attenuation factor matrix.
摘要翻译： 提供了一种用于解码低密度奇偶校验（LDPC）编码数据的低密度奇偶校验（LDPC）解码器，其中为LDPC奇偶校验矩阵的每一层提供层特定衰减因子。 包括多个系数的衰减因子矩阵指定每个层的特定衰减因子和解码过程的每次迭代。 校验节点处理器利用归一化分层最小和算法对与LDPC编码码字相关联的奇偶校验矩阵的每一层执行校验节点处理，其中最小和算法的衰减因子由衰减因子矩阵的系数确定 。
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5.发明授权公开(公告)号：US08935598B1
公开(公告)日：2015-01-13
申请号：US13797444
申请日：2013-03-12
申请人： PMC-Sierra US, Inc.
CPC分类号： H03M13/6583 , H03M13/112
摘要： A low-density parity check (LDPC) decoder is provided for decoding low-density parity check (LDPC) encoded data wherein an adaptive check node approximation is performed at the check node processor utilizing the smallest magnitude log-likelihood ratio (LLR) and the second smallest magnitude log-likelihood ratio (LLR) to adapt to the current conditions at the check node.
摘要翻译： 提供了一种用于解码低密度奇偶校验（LDPC）编码数据的低密度奇偶校验（LDPC）解码器，其中使用最小的幅度对数似然比（LLR）在校验节点处理器处执行自适应校验节点近似，并且 第二最小量级对数似然比（LLR），以适应校验节点处的当前条件。
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6.发明申请SYSTEM AND METHOD FOR HIGHER QUALITY LOG LIKELIHOOD RATIOS IN LDPC DECODING 有权用于LDPC解码中的高质量日志比特率的系统和方法公开(公告)号：US20140281800A1
公开(公告)日：2014-09-18
申请号：US14210067
申请日：2014-03-13
申请人： PMC-SIERRA US, INC.
发明人： Rino Micheloni , Alessia Marelli , Peter Z. Onufryk , Christopher I. W. Norrie , Ihab Jaser , Luca Crippa
IPC分类号： H03M13/11
CPC分类号： H03M13/1111 , G06F11/10 , G06F11/1012 , H03M13/15 , H03M13/255 , H03M13/3723 , H03M13/3927 , H04L1/0057
摘要： A nonvolatile memory storage controller is provided for delivering log likelihood ratios (LLRs) to a low-density parity check (LDPC) decoder for use in the decoding of an LDPC encoded codeword. The controller includes read circuitry for reading an LDPC encoded codeword stored in a nonvolatile memory storage module using a plurality of soft-decision reference voltages to provide a plurality of soft-decision bits representative of the codeword. The controller further includes a plurality of neighboring cell contribution LLR look-up tables representative of the contribution of the neighboring cells to threshold voltage distribution of the memory storage module. The controller provides the LLRs from the appropriate LLR look-up table to an LDPC decoder for the subsequent decoding of the codeword.
摘要翻译： 提供了一种非易失性存储器存储控制器，用于将对数似然比（LLR）传送到用于LDPC编码码字的解码中的低密度奇偶校验（LDPC）解码器。 控制器包括用于使用多个软判决参考电压读取存储在非易失性存储器存储模块中的LDPC编码码字的读取电路，以提供表示代码字的多个软判决位。 控制器还包括表示相邻小区对存储器存储模块的阈值电压分布的贡献的多个相邻小区贡献LLR查找表。 控制器将来自适当的LLR查找表的LLR提供给用于码字的后续解码的LDPC解码器。
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公开(公告)号：US09235488B2
公开(公告)日：2016-01-12
申请号：US14168222
申请日：2014-01-30
申请人： PMC-SIERRA US, INC.
CPC分类号： G06F11/2215 , G06F11/1012 , H03M13/1111 , H03M13/3905 , H03M13/3927
摘要： A random noise generation module for generating noisy LLRs for testing an error correction circuit of a nonvolatile memory storage module. The random noise generation module includes a coefficient generator for generating one or a plurality of coefficients, each of the plurality of coefficients associated with one region of a plurality of regions defining a linear space proportionately divided according to an area under a probability distribution curve for a nonvolatile memory storage module. The random noise generation module further includes a linear random number generator for generating a linear random number and a comparator for comparing the linear random number to one or more of the plurality of coefficients to identify the region of the plurality of regions of the probability distribution curve in which the linear random number belongs to generate a noisy LLR for testing an error correction circuit of a nonvolatile memory storage module.
摘要翻译： 一种随机噪声生成模块，用于产生用于测试非易失性存储器存储模块的纠错电路的噪声LLR。 所述随机噪声生成模块包括用于产生一个或多个系数的系数发生器，所述多个系数中的每一个与多个区域中的一个区域相关联，所述多个区域定义根据在概率分布曲线下的区域成比例地划分的线性空间 非易失性存储器存储模块。 随机噪声生成模块还包括用于生成线性随机数的线性随机数发生器和用于将线性随机数与多个系数中的一个或多个进行比较的比较器，以识别概率分布曲线的多个区域的区域 其中线性随机数属于产生用于测试非易失性存储器存储模块的纠错电路的噪声LLR。
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8.发明授权Apparatus and method based on LDPC codes for adjusting a correctable raw bit error rate limit in a memory system 有权基于LDPC码的装置和方法，用于调整存储器系统中可校正的原始误码率限制公开(公告)号：US09092353B1
公开(公告)日：2015-07-28
申请号：US13752885
申请日：2013-01-29
申请人： PMC-SIERRA US, INC.
CPC分类号： G06F11/1068 , G06F11/1008 , G11C29/52 , H03M13/11 , H03M13/1108 , H03M13/1111 , H03M13/116 , H03M13/2957 , H03M13/3715 , H03M13/45
摘要： Systems and methods for correcting errors in data read from memory cells include a memory controller, which includes an encoder, and a decoder. The memory controller is configured to adjust a correctable raw bit error rate limit to correct different bit error rates occurring in data read from the memory cells. The correctable raw bit error rate limit is adjusted by switching the decoding between hard-decision decoding and soft-decision decoding, wherein a number of soft bits allocated for message values can be changed during soft-decision decoding. The correctable raw bit error rate is adjusted by changing the code-rate within the memory system while making virtual adjustments to the same encoder and decoder.
摘要翻译： 用于校正从存储器单元读取的数据中的错误的系统和方法包括存储器控制器，其包括编码器和解码器。 存储器控制器被配置为调整可校正的原始误码率限制，以校正从存储器单元读取的数据中发生的不同位错误率。 通过切换硬判决解码和软判决解码之间的解码来调整可校正的原始误码率限制，其中在软判决解码期间可以改变分配给消息值的软比特数。 通过在对同一编码器和解码器进行虚拟调整的同时改变存储器系统内的码率来调整可校正的原始误码率。
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9.发明授权Apparatus and method for adjusting a correctable raw bit error rate limit in a memory system using strong log-likelihood (LLR) values 有权在使用强对数似然（LLR）值的存储器系统中调整可校正原始误码率限制的装置和方法公开(公告)号：US09128858B1
公开(公告)日：2015-09-08
申请号：US13752757
申请日：2013-01-29
申请人： PMC-SIERRA US, INC.
CPC分类号： G06F11/10 , G06F11/1048 , H03M13/09 , H03M13/1102 , H03M13/116 , H03M13/1194 , H03M13/1197 , H03M13/152 , H03M13/29 , H03M13/353 , H03M13/3707 , H03M13/3738 , H03M13/618
摘要： Apparatuses and methods for correcting errors in data read from memory cells of an integrated circuit device includes an encoder. The encoder is configured from a single parity check matrix and the encoder is configured to be virtually adjustable by setting a number of bits in the encoder to zero. A decoder is configured from the single parity check matrix and the decoder is configured to be virtually adjustable by setting a log-likelihood ratio (LLR) for a number of bits in the decoder to a strong value. A code-rate that the encoder and decoder uses can be changed by adjusting the number of bits in the encoder that are set to zero and the number of bits in the decoder that are set to the strong LLR value.
摘要翻译： 用于校正从集成电路装置的存储器单元读取的数据中的错误的装置和方法包括编码器。 编码器由单个奇偶校验矩阵配置，并且编码器被配置为通过将编码器中的位数设置为零而实际上可调节。 解码器由单个奇偶校验矩阵配置，并且解码器被配置为通过将解码器中的位数的对数似然比（LLR）设置为强值来实际可调节。 编码器和解码器使用的码率可以通过调整编码器中设置为零的位数和解码器中被设置为强LLR值的位数来改变。
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公开(公告)号：US20140281762A1
公开(公告)日：2014-09-18
申请号：US14168222
申请日：2014-01-30
申请人： PMC-SIERRA US, INC.
IPC分类号： G06F11/22
CPC分类号： G06F11/2215 , G06F11/1012 , H03M13/1111 , H03M13/3905 , H03M13/3927
摘要： A random noise generation module for generating noisy LLRs for testing an error correction circuit of a nonvolatile memory storage module. The random noise generation module includes a coefficient generator for generating one or a plurality of coefficients, each of the plurality of coefficients associated with one region of a plurality of regions defining a linear space proportionately divided according to an area under a probability distribution curve for a nonvolatile memory storage module. The random noise generation module further includes a linear random number generator for generating a linear random number and a comparator for comparing the linear random number to one or more of the plurality of coefficients to identify the region of the plurality of regions of the probability distribution curve in which the linear random number belongs to generate a noisy LLR for testing an error correction circuit of a nonvolatile memory storage module.
摘要翻译： 一种随机噪声生成模块，用于产生用于测试非易失性存储器存储模块的纠错电路的噪声LLR。 所述随机噪声生成模块包括用于产生一个或多个系数的系数发生器，所述多个系数中的每一个与多个区域中的一个区域相关联，所述多个区域定义根据在概率分布曲线下的区域成比例地划分的线性空间 非易失性存储器存储模块。 随机噪声生成模块还包括用于生成线性随机数的线性随机数发生器和用于将线性随机数与多个系数中的一个或多个进行比较的比较器，以识别概率分布曲线的多个区域的区域 其中线性随机数属于产生用于测试非易失性存储器存储模块的纠错电路的噪声LLR。
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