公开(公告)号：US20060283709A1

公开(公告)日：2006-12-21

申请号：US11155495

申请日：2005-06-20

申请人： Panayotis Andricacos ,  Emanuel Cooper ,  John Cotte ,  Hariklia Deligianni ,  Caliopo Andricacos

发明人： Panayotis Andricacos ,  Emanuel Cooper ,  John Cotte ,  Hariklia Deligianni ,  Caliopo Andricacos

IPC分类号： C25C7/02

CPC分类号： C25D17/10 ,  C25D11/02 ,  C25D17/12

摘要： Various counter-electrodes for electroplating, electrodeposition or anodizing of substrates are disclosed. According to certain embodiments, multi-segmented counter-electrodes are provided. According to additional embodiments, counter-electrodes having concave or convex top surfaces are provided. The disclosed counter-electrodes enable greater control over electrodeposition, electroetching and anodizing processes for resistive substrates, as well as more uniform plating and etching of resistive substrates. Methods for electroplating, electrodeposition or anodizing of resistive substrates using multi-segmented counter-electrodes are also provided.

摘要翻译： 公开了用于电镀，电沉积或阳极氧化基板的各种对电极。 根据某些实施例，提供多段对置电极。 根据另外的实施例，提供具有凹面或凸面顶面的对电极。 所公开的对电极能够更好地控制电沉积，电蚀和阳极氧化工艺的电阻衬底，以及更均匀的电镀和蚀刻电阻衬底。 还提供了使用多分段对电极的电镀，电沉积或阳极氧化电阻基板的方法。

公开(公告)号：US20060163083A1

公开(公告)日：2006-07-27

申请号：US11038236

申请日：2005-01-21

申请人： Panayotis Andricacos ,  Donald Canaperi ,  Emanuel Cooper ,  John Cotte ,  Hariklia Deligianni ,  Laertis Economikos ,  Daniel Edelstein ,  Silvia Franz ,  Balasubramanian Pranatharthiharan ,  Mahadevaiyer Krishnan ,  Andrew Mansson ,  Erick Walton ,  Alan West ,  Caliopi Andricacos

发明人： Panayotis Andricacos ,  Donald Canaperi ,  Emanuel Cooper ,  John Cotte ,  Hariklia Deligianni ,  Laertis Economikos ,  Daniel Edelstein ,  Silvia Franz ,  Balasubramanian Pranatharthiharan ,  Mahadevaiyer Krishnan ,  Andrew Mansson ,  Erick Walton ,  Alan West ,  Caliopi Andricacos

IPC分类号： B23H3/00

CPC分类号： C25F3/02 ,  B23H5/08 ,  C09G1/04 ,  H01L21/32125

摘要： Methods and compositions for electro-chemical-mechanical polishing (e-CMP) of silicon chip interconnect materials, such as copper, are provided. The methods include the use of compositions according to the invention in combination with pads having various configurations.

摘要翻译： 提供了诸如铜之类的硅芯片互连材料的电化学机械抛光（e-CMP）的方法和组合物。 所述方法包括使用根据本发明的组合物与具有各种构型的垫组合。

公开(公告)号：US20060081885A1

公开(公告)日：2006-04-20

申请号：US11228269

申请日：2005-10-26

申请人： Katherine Saenger ,  Cyril Cabral ,  Hariklia Deligianni ,  Panayotis Andricacos ,  Caliopi Andricacos ,  Philippe Vereecken ,  Emanuel Cooper

发明人： Katherine Saenger ,  Cyril Cabral ,  Hariklia Deligianni ,  Panayotis Andricacos ,  Caliopi Andricacos ,  Philippe Vereecken ,  Emanuel Cooper

IPC分类号： H01L29/76 ,  H01L29/745

CPC分类号： H01L21/28088 ,  H01L29/4966 ,  H01L29/66621 ,  H01L29/7834

摘要： Disclosed is a method for making a metal gate for a FET, wherein the metal gate comprises at least some material deposited by electroplating as well as an FET device comprising a metal gate that is at least partially plated. Further disclosed is a method for making a metal gate for a FET wherein the metal gate comprises at least some plated material and the method comprises the steps of: selecting a substrate having a top surface and a recessed region; conformally depositing a thin conductive seed layer on the substrate; and electroplating a filler gate metal on the seed layer to fill and overfill the recessed region.

摘要翻译： 公开了一种用于制造用于FET的金属栅极的方法，其中金属栅极包括通过电镀沉积的至少一些材料以及包括至少部分镀覆的金属栅极的FET器件。 还公开了一种用于制造用于FET的金属栅极的方法，其中金属栅极包括至少一些镀层材料，并且该方法包括以下步骤：选择具有顶表面和凹陷区域的衬底; 在衬底上共形沉积导电种子层; 并在种子层上电镀填充栅极金属以填充和覆盖凹陷区域。

公开(公告)号：US20050095852A1

公开(公告)日：2005-05-05

申请号：US10694793

申请日：2003-10-29

申请人： Katherine Saenger ,  Cyril Cabral ,  Emanuel Cooper ,  Hariklia Deligianni ,  Panayotis Andricacos ,  Philippe Vereecken

发明人： Katherine Saenger ,  Cyril Cabral ,  Emanuel Cooper ,  Hariklia Deligianni ,  Panayotis Andricacos ,  Philippe Vereecken

IPC分类号： H01L21/28 ,  H01L21/288 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L29/745 ,  H01L21/44 ,  H01L29/76

CPC分类号： H01L21/28088 ,  H01L29/4966 ,  H01L29/66621 ,  H01L29/7834

摘要： Disclosed is a method for making a metal gate for a FET, wherein the metal gate comprises at least some material deposited by electroplating as well as an FET device comprising a metal gate that is at least partially plated. Further disclosed is a method for making a metal gate for a FET wherein the metal gate comprises at least some plated material and the method comprises the steps of: selecting a substrate having a top surface and a recessed region; conformally depositing a thin conductive seed layer on the substrate; and electroplating a filler gate metal on the seed layer to fill and overfill the recessed region.

摘要翻译： 公开了一种用于制造用于FET的金属栅极的方法，其中金属栅极包括通过电镀沉积的至少一些材料以及包括至少部分镀覆的金属栅极的FET器件。 还公开了一种用于制造用于FET的金属栅极的方法，其中金属栅极包括至少一些电镀材料，并且该方法包括以下步骤：选择具有顶表面和凹陷区域的衬底; 在衬底上共形沉积导电种子层; 并在种子层上电镀填充栅极金属以填充和覆盖凹陷区域。

公开(公告)号：US20060076685A1

公开(公告)日：2006-04-13

申请号：US11265302

申请日：2005-11-03

申请人： Panayotis Andricacos ,  Shyng-Tsong Chen ,  John Cotte ,  Hariklia Deligianni ,  Mahadevaiyer Krishnan ,  Wei-Tsu Tseng ,  Philippe Vereecken

发明人： Panayotis Andricacos ,  Shyng-Tsong Chen ,  John Cotte ,  Hariklia Deligianni ,  Mahadevaiyer Krishnan ,  Wei-Tsu Tseng ,  Philippe Vereecken

IPC分类号： H01L23/48

CPC分类号： H01L21/76846 ,  H01L21/2885 ,  H01L21/6708 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76874 ,  H01L21/76883

摘要： Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for addressing the problem of an increased resistive path as electrolyte during electroetching and/or electroplating flows from the wafer edge inwards is provided.

公开(公告)号：US20050167780A1

公开(公告)日：2005-08-04

申请号：US10768773

申请日：2004-01-29

申请人： Daniel Edelstein ,  Panayotis Andricacos ,  John Cotte ,  Hariklia Deligianni ,  John Magerlein ,  Kevin Petrarca ,  Kenneth Stein ,  Richard Volant

发明人： Daniel Edelstein ,  Panayotis Andricacos ,  John Cotte ,  Hariklia Deligianni ,  John Magerlein ,  Kevin Petrarca ,  Kenneth Stein ,  Richard Volant

IPC分类号： H01F41/04 ,  H01F17/00 ,  H01L21/02 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L27/08 ,  H01L23/48 ,  H01L21/8222

CPC分类号： H01L24/12 ,  H01L23/5227 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L27/08 ,  H01L28/10 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05014 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05084 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

摘要： An inductor and a method of forming and the inductor, the method including: (a) providing a semiconductor substrate; (b) forming a dielectric layer on a top surface of the substrate; (c) forming a lower trench in the dielectric layer; (d) forming a resist layer on a top surface of the dielectric layer; (e) forming an upper trench in the resist layer, the upper trench aligned to the lower trench, a bottom of the upper trench open to the lower trench; and (f) completely filling the lower trench at least partially filling the upper trench with a conductor in order to form the inductor. The inductor including a top surface, a bottom surface and sidewalls, a lower portion of said inductor extending a fixed distance into a dielectric layer formed on a semiconductor substrate and an upper portion extending above said dielectric layer; and means to electrically contact said inductor.

摘要翻译： 一种电感器及其形成方法和电感器，所述方法包括：（a）提供半导体衬底; （b）在所述基板的顶表面上形成电介质层; （c）在介电层中形成下沟槽; （d）在介电层的顶表面上形成抗蚀剂层; （e）在所述抗蚀剂层中形成上沟槽，所述上沟槽对准所述下沟槽，所述上沟槽的底部通向所述下沟槽; 和（f）用导体完全填充下沟槽至少部分地填充上沟槽，以形成电感器。 所述电感器包括顶表面，底表面和侧壁，所述电感器的下部将固定距离延伸到形成在半导体衬底上的电介质层和在所述电介质层上方延伸的上部; 以及用于电接触所述电感器的装置。

公开(公告)号：US20060105534A1

公开(公告)日：2006-05-18

申请号：US11320375

申请日：2005-12-28

申请人： Daniel Edelstein ,  Panayotis Andricacos ,  John Cotte ,  Hariklia Deligianni ,  John Magerlein ,  Kevin Petrarca ,  Kenneth Stein ,  Richard Volant

发明人： Daniel Edelstein ,  Panayotis Andricacos ,  John Cotte ,  Hariklia Deligianni ,  John Magerlein ,  Kevin Petrarca ,  Kenneth Stein ,  Richard Volant

IPC分类号： H01L21/8222

CPC分类号： H01L24/12 ,  H01L23/5227 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L27/08 ,  H01L28/10 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05014 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05084 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

摘要： An inductor and a method of forming and the inductor, the method including: (a) forming a dielectric layer on a top surface of a substrate; (b) forming a lower trench in the dielectric layer; (c) forming a resist layer on a top surface of the dielectric layer; (d) forming an upper trench in the resist layer, the upper trench aligned to the lower trench, a bottom of the upper trench open to the lower trench; and (e) completely filling the lower trench at least partially filling the upper trench with a conductor in order to form the inductor. The inductor including a top surface, a bottom surface and sidewalls, a lower portion of said inductor extending a fixed distance into a dielectric layer formed on a semiconductor substrate and an upper portion extending above said dielectric layer; and means to electrically contact said inductor.

摘要翻译： 一种电感器及其形成方法和电感器，所述方法包括：（a）在基板的顶表面上形成电介质层; （b）在介电层中形成下沟槽; （c）在介电层的顶表面上形成抗蚀剂层; （d）在抗蚀剂层中形成上沟槽，上沟槽与下沟槽对准，上沟槽的底部通向下沟槽; 和（e）用导体完全填充下沟槽至少部分地填充上沟槽，以形成电感器。 所述电感器包括顶表面，底表面和侧壁，所述电感器的下部将固定距离延伸到形成在半导体衬底上的电介质层和在所述电介质层上方延伸的上部; 以及用于电接触所述电感器的装置。

公开(公告)号：US20050037608A1

公开(公告)日：2005-02-17

申请号：US10639989

申请日：2003-08-13

申请人： Panayotis Andricacos ,  Emanuel Cooper ,  Timothy Dalton ,  Hariklia Deligianni ,  Daniel Guidotti ,  Keith Kwietniak ,  Michelle Steen ,  Cornelia Tsang

发明人： Panayotis Andricacos ,  Emanuel Cooper ,  Timothy Dalton ,  Hariklia Deligianni ,  Daniel Guidotti ,  Keith Kwietniak ,  Michelle Steen ,  Cornelia Tsang

IPC分类号： H01L21/288 ,  H01L21/3065 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/2885 ,  H01L21/30655 ,  H01L21/76898

摘要： Flared and non-flared metallized deep vias having aspect ratios of about 2 or greater are provided. Blind vias have been fabricated in silicon substrates up to a depth of about 300 microns, and flared through vias have been fabricated up to about 750 microns, the approximate thickness of a silicon substrate wafer, enabling the formation of electrical connections at either or both ends of a via. In spite of the depth and high aspect ratios attainable, the etched vias are completely filled with plated copper conductor, completing the formation of deep vias and allowing fuller use of both sides of the substrate.

摘要翻译： 提供具有约2或更大的纵横比的扩张和未扩口的金属化深通孔。 盲孔已经在硅衬底中制造达到约300微米的深度，并且通过通孔已经被制造高达约750微米，硅衬底晶片的大致厚度，使得能够在两端或两端形成电连接 的通道。 尽管可以获得深度和高纵横比，但是蚀刻的通孔完全被电镀铜导体填充，从而形成深通孔并允许更充分地使用基板的两侧。

公开(公告)号：US20060164194A1

公开(公告)日：2006-07-27

申请号：US11358823

申请日：2006-02-21

申请人： Hariklia Deligianni ,  Panayotis Andricacos ,  L. Paivikki Buchwalter ,  John Cotte ,  Christopher Jahnes ,  Mahadevaiyer Krishnan ,  John Magerlein ,  Kenneth Stein ,  Richard Volant ,  James Tornello ,  Jennifer Lund

发明人： Hariklia Deligianni ,  Panayotis Andricacos ,  L. Paivikki Buchwalter ,  John Cotte ,  Christopher Jahnes ,  Mahadevaiyer Krishnan ,  John Magerlein ,  Kenneth Stein ,  Richard Volant ,  James Tornello ,  Jennifer Lund

IPC分类号： H01H51/22

CPC分类号： H01H59/0009 ,  H01H2001/0052 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49204

摘要： A semiconductor micro-electromechanical system (MEMS) switch provided with noble metal contacts that act as an oxygen barrier to copper electrodes is described. The MEMS switch is fully integrated into a CMOS semiconductor fabrication line. The integration techniques, materials and processes are fully compatible with copper chip metallization processes and are typically, a low cost and a low temperature process (below 400° C.). The MEMS switch includes: a movable beam within a cavity, the movable beam being anchored to a wall of the cavity at one or both ends of the beam; a first electrode embedded in the movable beam; and a second electrode embedded in an wall of the cavity and facing the first electrode, wherein the first and second electrodes are respectively capped by the noble metal contact.

摘要翻译： 描述了提供有作为铜电极的氧阻隔的贵金属触点的半导体微机电系统（MEMS）开关。 MEMS开关完全集成到CMOS半导体制造线中。 集成技术，材料和工艺完全兼容铜芯片金属化工艺，通常是低成本和低温工艺（低于400℃）。 MEMS开关包括：在空腔内的可移动光束，可移动光束在光束的一端或两端锚定到空腔的壁; 嵌入可移动光束中的第一电极; 以及第二电极，其嵌入在所述空腔的壁中并且面向所述第一电极，其中所述第一和第二电极分别被所述贵金属接触物覆盖。

公开(公告)号：US20050007217A1

公开(公告)日：2005-01-13

申请号：US10604278

申请日：2003-07-08

申请人： Hariklia Deligianni ,  Panayotis Andricacos ,  L. Buchwalter ,  John Cotte ,  Christopher Jahnes ,  Mahadevaiyer Krishnan ,  John Magerlein ,  Kenneth Stein ,  Richard Volant ,  James Tornello ,  Jennifer Lund

发明人： Hariklia Deligianni ,  Panayotis Andricacos ,  L. Buchwalter ,  John Cotte ,  Christopher Jahnes ,  Mahadevaiyer Krishnan ,  John Magerlein ,  Kenneth Stein ,  Richard Volant ,  James Tornello ,  Jennifer Lund

IPC分类号： H01H59/00 ,  H01H51/22

CPC分类号： H01H59/0009 ,  H01H2001/0052 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49204

摘要： A semiconductor micro-electromechanical system (MEMS) switch provided with noble metal contacts that act as an oxygen barrier to copper electrodes is described. The MEMS switch is fully integrated into a CMOS semiconductor fabrication line. The integration techniques, materials and processes are fully compatible with copper chip metallization processes and are typically, a low cost and a low temperature process (below 400°0 C.). The MEMS switch includes: a movable beam within a cavity, the movable beam being anchored to a wall of the cavity at one or both ends of the beam; a first electrode embedded in the movable beam; and a second electrode embedded in an wall of the cavity and facing the first electrode, wherein the first and second electrodes are respectively capped by the noble metal contact.

摘要翻译： 描述了提供有作为铜电极的氧阻隔的贵金属触点的半导体微机电系统（MEMS）开关。 MEMS开关完全集成到CMOS半导体制造线中。 集成技术，材料和工艺完全兼容铜芯片金属化工艺，通常是低成本和低温工艺（低于400°C）。 MEMS开关包括：在空腔内的可移动光束，可移动光束在光束的一端或两端锚定到空腔的壁; 嵌入可移动光束中的第一电极; 以及第二电极，其嵌入在所述空腔的壁中并且面向所述第一电极，其中所述第一和第二电极分别被所述贵金属接触物覆盖。