公开(公告)号：US20100051474A1

公开(公告)日：2010-03-04

申请号：US12548893

申请日：2009-08-27

申请人： Panayotis C. Andricacos ,  Caliopi Andricacos ,  Donald F. Canaperi ,  Emanuel I. Cooper ,  John M. Cotte ,  Hariklia Deligianni ,  Laertis Economikos ,  Daniel C. Edelstein ,  Silvia Franz ,  Balasubramanian Pranatharthiharan ,  Mahadevaiyer Krishnan ,  Andrew P. Mansson ,  Erick G. Walton ,  Alan C. West

发明人： Panayotis C. Andricacos ,  Caliopi Andricacos ,  Donald F. Canaperi ,  Emanuel I. Cooper ,  John M. Cotte ,  Hariklia Deligianni ,  Laertis Economikos ,  Daniel C. Edelstein ,  Silvia Franz ,  Balasubramanian Pranatharthiharan ,  Mahadevaiyer Krishnan ,  Andrew P. Mansson ,  Erick G. Walton ,  Alan C. West

IPC分类号： B23H5/06

CPC分类号： C25F3/02 ,  B23H5/08 ,  C09G1/04 ,  H01L21/32125

摘要： Methods and compositions for electro-chemical-mechanical polishing (e-CMP) of silicon chip interconnect materials, such as copper, are provided. The methods include the use of compositions according to the invention in combination with pads having various configurations.

摘要翻译： 提供了诸如铜之类的硅芯片互连材料的电化学机械抛光（e-CMP）的方法和组合物。 所述方法包括使用根据本发明的组合物与具有各种构型的垫组合。

公开(公告)号：US20060163083A1

公开(公告)日：2006-07-27

申请号：US11038236

申请日：2005-01-21

申请人： Panayotis Andricacos ,  Donald Canaperi ,  Emanuel Cooper ,  John Cotte ,  Hariklia Deligianni ,  Laertis Economikos ,  Daniel Edelstein ,  Silvia Franz ,  Balasubramanian Pranatharthiharan ,  Mahadevaiyer Krishnan ,  Andrew Mansson ,  Erick Walton ,  Alan West ,  Caliopi Andricacos

发明人： Panayotis Andricacos ,  Donald Canaperi ,  Emanuel Cooper ,  John Cotte ,  Hariklia Deligianni ,  Laertis Economikos ,  Daniel Edelstein ,  Silvia Franz ,  Balasubramanian Pranatharthiharan ,  Mahadevaiyer Krishnan ,  Andrew Mansson ,  Erick Walton ,  Alan West ,  Caliopi Andricacos

IPC分类号： B23H3/00

CPC分类号： C25F3/02 ,  B23H5/08 ,  C09G1/04 ,  H01L21/32125

摘要： Methods and compositions for electro-chemical-mechanical polishing (e-CMP) of silicon chip interconnect materials, such as copper, are provided. The methods include the use of compositions according to the invention in combination with pads having various configurations.

摘要翻译： 提供了诸如铜之类的硅芯片互连材料的电化学机械抛光（e-CMP）的方法和组合物。 所述方法包括使用根据本发明的组合物与具有各种构型的垫组合。

公开(公告)号：US06776885B2

公开(公告)日：2004-08-17

申请号：US10294199

申请日：2002-11-14

申请人： Laertis Economikos ,  Hariklia Deligianni ,  John M. Cotte ,  Panayotis C. Andricacos

发明人： Laertis Economikos ,  Hariklia Deligianni ,  John M. Cotte ,  Panayotis C. Andricacos

IPC分类号： C25D1400

CPC分类号： C25D5/48 ,  C25D17/00 ,  C25D17/001 ,  C25D17/10

摘要： An apparatus for plating and planarizing metal on a substrate includes a plurality of dispensing segments, each having at least one hole for dispensing electroplating solution onto the substrate. The dispensing segments form a circular counterelectrode and are movable with respect to each other during an electroplating process, so that the counterelectrode has a variable diameter. The electroplating solution is thus dispensed on an annular portion of the substrate having a diameter corresponding to the diameter of the counterelectrode; accordingly, the variable-diameter counterelectrode permits localized delivery of the plating solution to the substrate.

摘要翻译： 用于在基底上电镀和平面化金属的装置包括多个分配段，每个分配段具有至少一个用于将电镀溶液分配到衬底上的孔。 分配段形成圆形反电极并且可以在电镀过程期间相对于彼此移动，使得反电极具有可变的直径。 因此，电镀溶液被分配在具有对应于反电极的直径的直径的基底的环形部分上; 因此，可变直径对电极允许将电镀液局部输送到基板。

公开(公告)号：US07190079B2

公开(公告)日：2007-03-13

申请号：US11265302

申请日：2005-11-03

申请人： Panayotis C. Andricacos ,  Shyng-Tsong Chen ,  John M. Cotte ,  Hariklia Deligianni ,  Mahadevaiyer Krishnan ,  Wei-Tsu Tseng ,  Philippe M. Vereecken

发明人： Panayotis C. Andricacos ,  Shyng-Tsong Chen ,  John M. Cotte ,  Hariklia Deligianni ,  Mahadevaiyer Krishnan ,  Wei-Tsu Tseng ,  Philippe M. Vereecken

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L21/76846 ,  H01L21/2885 ,  H01L21/6708 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76874 ,  H01L21/76883

摘要： Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for addressing the problem of an increased resistive path as electrolyte during electroetching and/or electroplating flows from the wafer edge inwards is provided.

摘要翻译： 通过在衬垫材料的存在下使用选择性蚀刻和/或选择性电镀选择性地封盖铜来制造图案化的铜结构。 提供了用于解决在电蚀和/或电镀过程中作为电解质增加的电阻路径从晶片边缘向内流动的问题的装置。

公开(公告)号：US07008871B2

公开(公告)日：2006-03-07

申请号：US10611931

申请日：2003-07-03

申请人： Panayotis C. Andricacos ,  Shyng-Tsong Chen ,  John M. Cotte ,  Hariklia Deligianni ,  Mahadevaiyer Krishnan ,  Wei-Tsu Tseng ,  Philippe M. Vereecken

发明人： Panayotis C. Andricacos ,  Shyng-Tsong Chen ,  John M. Cotte ,  Hariklia Deligianni ,  Mahadevaiyer Krishnan ,  Wei-Tsu Tseng ,  Philippe M. Vereecken

IPC分类号： H01L21/44

CPC分类号： H01L21/76846 ,  H01L21/2885 ,  H01L21/6708 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76874 ,  H01L21/76883

摘要： Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for addressing the problem of an increased resistive path as electrolyte during electroetching and/or electroplating flows from the wafer edge inwards is provided.

摘要翻译： 通过在衬垫材料的存在下使用选择性蚀刻和/或选择性电镀选择性地封盖铜来制造图案化的铜结构。 提供了用于解决在电蚀和/或电镀过程中作为电解质增加的电阻路径从晶片边缘向内流动的问题的装置。

公开(公告)号：US20100047990A1

公开(公告)日：2010-02-25

申请号：US12612743

申请日：2009-11-05

申请人： Daniel C. Edelstein ,  Panayotis C. Andricacos ,  John M. Cotte ,  Hariklia Deligianni ,  John H. Magerlein ,  Kevin S. Petrarca ,  Kenneth J. Stein ,  Richard P. Volant

发明人： Daniel C. Edelstein ,  Panayotis C. Andricacos ,  John M. Cotte ,  Hariklia Deligianni ,  John H. Magerlein ,  Kevin S. Petrarca ,  Kenneth J. Stein ,  Richard P. Volant

IPC分类号： H01L21/02

CPC分类号： H01L24/12 ,  H01L23/5227 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L27/08 ,  H01L28/10 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05014 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05084 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method of forming an inductor. The method including: (a) forming a dielectric layer on a top surface of a substrate; after (a), (b) forming a lower trench in the dielectric layer; after (b), (c) forming a resist layer on a top surface of the dielectric layer; after (c), (d) forming an upper trench in the resist layer, the upper trench aligned to the lower trench, a bottom of the upper trench open to the lower trench; and after (d), (e) completely filling the lower trench and at least partially filling the upper trench with a conductor in order to form the inductor.

摘要翻译： 一种形成电感器的方法。 该方法包括：（a）在基板的顶表面上形成电介质层; （a）之后，（b）在介电层中形成下沟槽; （b）之后，（c）在介电层的顶表面上形成抗蚀剂层; 在（c）之后，（d）在抗蚀剂层中形成上沟槽，上沟槽与下沟槽对准，上沟槽的底部通向下沟槽; （d）之后，（e）完全填充下沟槽并且用导体至少部分地填充上沟槽以形成电感器。

公开(公告)号：US07638406B2

公开(公告)日：2009-12-29

申请号：US11320375

申请日：2005-12-28

申请人： Daniel C. Edelstein ,  Panayotis C. Andricacos ,  John M. Cotte ,  Hariklia Deligianni ,  John H. Magerlein ,  Kevin S. Petrarca ,  Kenneth J. Stein ,  Richard P. Volant

发明人： Daniel C. Edelstein ,  Panayotis C. Andricacos ,  John M. Cotte ,  Hariklia Deligianni ,  John H. Magerlein ,  Kevin S. Petrarca ,  Kenneth J. Stein ,  Richard P. Volant

IPC分类号： H01L21/20

CPC分类号： H01L24/12 ,  H01L23/5227 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L27/08 ,  H01L28/10 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05014 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05084 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method of forming an inductor. The method includes: forming a dielectric layer on a substrate; forming a lower trench in the dielectric layer; forming a liner in the lower trench and on the dielectric layer; forming a Cu seed layer over the liner; forming a resist layer on the Cu seed layer; forming an upper trench in the resist layer; electroplating Cu to completely fill the lower trench and at least partially fill the upper trench; removing the resist layer; selectively forming a passivation layer on all exposed Cu surfaces; selectively removing the Cu seed layer from regions of the liner; and removing the thus exposed regions of the liner from the dielectric layer, wherein a top surface of the inductor extends above a top surface of the dielectric layer, the passivation layer remaining on regions of sidewalls of the inductor above the top surface of the dielectric layer.

摘要翻译： 一种形成电感器的方法。 该方法包括：在基板上形成电介质层; 在介电层中形成下沟槽; 在下沟槽和电介质层上形成衬垫; 在衬套上形成Cu籽晶层; 在Cu籽晶层上形成抗蚀剂层; 在抗蚀剂层中形成上沟槽; 电镀Cu以完全填充下沟槽并且至少部分地填充上沟槽; 去除抗蚀剂层; 在所有暴露的Cu表面上选择性地形成钝化层; 从所述衬垫的区域选择性地去除所述Cu籽晶层; 以及从所述电介质层去除所述衬垫的这样暴露的区域，其中所述电感器的顶表面延伸到所述电介质层的顶表面之上，所述钝化层保留在所述电介质的位于所述电介质层的顶表面之上的侧壁的区域上 。

公开(公告)号：US07829427B2

公开(公告)日：2010-11-09

申请号：US12612743

申请日：2009-11-05

申请人： Daniel C. Edelstein ,  Panayotis C. Andricacos ,  John M. Cotte ,  Hariklia Deligianni ,  John H. Magerlein ,  Kevin S. Petrarca ,  Kenneth J. Stein ,  Richard P. Volant

发明人： Daniel C. Edelstein ,  Panayotis C. Andricacos ,  John M. Cotte ,  Hariklia Deligianni ,  John H. Magerlein ,  Kevin S. Petrarca ,  Kenneth J. Stein ,  Richard P. Volant

IPC分类号： H01L21/20

CPC分类号： H01L24/12 ,  H01L23/5227 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L27/08 ,  H01L28/10 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05014 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05084 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method of forming an inductor. The method including: (a) forming a dielectric layer on a top surface of a substrate; after (a), (b) forming a lower trench in the dielectric layer; after (b), (c) forming a resist layer on a top surface of the dielectric layer; after (c), (d) forming an upper trench in the resist layer, the upper trench aligned to the lower trench, a bottom of the upper trench open to the lower trench; and after (d), (e) completely filling the lower trench and at least partially filling the upper trench with a conductor in order to form the inductor.

摘要翻译： 一种形成电感器的方法。 该方法包括：（a）在基板的顶表面上形成电介质层; （a）之后，（b）在介电层中形成下沟槽; （b）之后，（c）在介电层的顶表面上形成抗蚀剂层; 在（c）之后，（d）在抗蚀剂层中形成上沟槽，上沟槽与下沟槽对准，上沟槽的底部通向下沟槽; 在（d）之后，（e）完全填充下沟槽并且用导体至少部分地填充上沟槽以形成电感器。

公开(公告)号：US07068138B2

公开(公告)日：2006-06-27

申请号：US10768773

申请日：2004-01-29

申请人： Daniel C. Edelstein ,  Panayotis C. Andricacos ,  John M. Cotte ,  Hariklia Deligianni ,  John H. Magerlein ,  Kevin S. Petrarca ,  Kenneth J. Stein ,  Richard P. Volant

发明人： Daniel C. Edelstein ,  Panayotis C. Andricacos ,  John M. Cotte ,  Hariklia Deligianni ,  John H. Magerlein ,  Kevin S. Petrarca ,  Kenneth J. Stein ,  Richard P. Volant

IPC分类号： H01F27/24

CPC分类号： H01L24/12 ,  H01L23/5227 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L27/08 ,  H01L28/10 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05014 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05084 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

摘要： An inductor and a method of forming and the inductor, the method including: (a) providing a semiconductor substrate; (b) forming a dielectric layer on a top surface of the substrate; (c) forming a lower trench in the dielectric layer; (d) forming a resist layer on a top surface of the dielectric layer; (e) forming an upper trench in the resist layer, the upper trench aligned to the lower trench, a bottom of the upper trench open to the lower trench; and (f) completely filling the lower trench at least partially filling the upper trench with a conductor in order to form the inductor. The inductor including a top surface, a bottom surface and sidewalls, a lower portion of said inductor extending a fixed distance into a dielectric layer formed on a semiconductor substrate and an upper portion extending above said dielectric layer; and means to electrically contact said inductor.

摘要翻译： 一种电感器及其形成方法和电感器，所述方法包括：（a）提供半导体衬底; （b）在所述基板的顶表面上形成电介质层; （c）在介电层中形成下沟槽; （d）在介电层的顶表面上形成抗蚀剂层; （e）在所述抗蚀剂层中形成上沟槽，所述上沟槽对准所述下沟槽，所述上沟槽的底部通向所述下沟槽; 和（f）用导体完全填充下沟槽至少部分地填充上沟槽，以形成电感器。 所述电感器包括顶表面，底表面和侧壁，所述电感器的下部将固定距离延伸到形成在半导体衬底上的电介质层和在所述电介质层上方延伸的上部; 以及用于电接触所述电感器的装置。

公开(公告)号：US07227265B2

公开(公告)日：2007-06-05

申请号：US10810719

申请日：2004-03-29

申请人： Panayotis C. Andricacos ,  Steven H. Boettcher ,  Dean S. Chung ,  Hariklia Deligianni ,  James E. Fluegel ,  Wilma Jean Horkans ,  Keith T. Kwietniak ,  Peter S. Locke ,  Christopher C. Parks ,  Soon-Cheon Seo ,  Andrew H. Simon ,  Erick G. Walton

发明人： Panayotis C. Andricacos ,  Steven H. Boettcher ,  Dean S. Chung ,  Hariklia Deligianni ,  James E. Fluegel ,  Wilma Jean Horkans ,  Keith T. Kwietniak ,  Peter S. Locke ,  Christopher C. Parks ,  Soon-Cheon Seo ,  Andrew H. Simon ,  Erick G. Walton

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/2885 ,  C25D3/38 ,  C25D5/024 ,  C25D5/18 ,  C25D7/123 ,  H01L21/76877

摘要： Interconnect structures with copper conductors being at least substantially free of internal seams or voids are obtained employing an electroplating copper bath containing dissolved cupric salt wherein the concentration of the salt is at least about 0.4 molar and up to about 0.5 molar concentration of an acid. Also provided are copper damascene structures having an aspect ratio of greater than about 3 and a width of less than about 0.275 μm and via openings filled with electroplated copper than is substantially free of internal seams or voids.

摘要翻译： 使用包含溶解的铜盐的电镀铜浴获得至少基本上不含内部接缝或空隙的铜导体的互连结构，其中盐的浓度为酸的至少约0.4摩尔浓度至高达约0.5摩尔浓度。 还提供了具有大于约3的宽高比和小于约0.275μm的宽度的铜镶嵌结构以及填充有电镀铜的通孔，基本上不含内部接缝或空隙。