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    Apparatus for accurate and efficient quality and reliability evaluation of micro electromechanical systems
    4.
    发明授权
    Apparatus for accurate and efficient quality and reliability evaluation of micro electromechanical systems 失效
    微机电系统的准确高效的质量和可靠性评估装置

    公开(公告)号：US07602265B2

    公开(公告)日：2009-10-13

    申请号：US11163485

    申请日：2005-10-20

    申请人： Hariklia Deligianni ,  Robert D. Edwards ,  Thomas J. Fleischman ,  Robert A. Groves ,  Charles J. Montrose ,  Richard P. Volant ,  Ping-Chuan Wang

    发明人： Hariklia Deligianni ,  Robert D. Edwards ,  Thomas J. Fleischman ,  Robert A. Groves ,  Charles J. Montrose ,  Richard P. Volant ,  Ping-Chuan Wang

    IPC分类号： H01H51/22

    CPC分类号： H01H59/0009

    摘要： The present invention provides multiple test structures for performing reliability and qualification tests on MEMS switch devices. A Test structure for contact and gap characteristic measurements is employed having a serpentine layout simulates rows of upper and lower actuation electrodes. A cascaded switch chain test is used to monitor process defects with large sample sizes. A ring oscillator is used to measure switch speed and switch lifetime. A resistor ladder test structure is configured having each resistor in series with a switch to be tested, and having each switch-resistor pair electrically connected in parallel. Serial/parallel test structures are proposed with MEMS switches working in tandem with switches of established technology. A shift register is used to monitor the open and close state of the MEMS switches. Pull-in voltage, drop-out voltage, activation leakage current, and switch lifetime measurements are performed using the shift register.

    摘要翻译： 本发明提供用于在MEMS开关装置上执行可靠性和鉴定测试的多个测试结构。 采用具有蛇形布局的接触和间隙特性测量的测试结构来模拟上下驱动电极的行。 级联交换链测试用于监控大样本量的过程缺陷。 环形振荡器用于测量开关速度和开关寿命。 电阻梯形测试结构被配置为具有与要测试的开关串联的每个电阻器，并且每个开关电阻器对并联电连接。 提出了串联/并联测试结构，其中MEMS开关与成熟技术的开关串联工作。 移位寄存器用于监测MEMS开关的开启和关闭状态。 使用移位寄存器执行拉入电压，掉电电压，启动漏电流和开关寿命测量。

    APPARATUS FOR ACCURATE AND EFFICIENT QUALITY AND RELIABILITY EVALUATION OF MICRO ELECTROMECHANICAL SYSTEMS
    5.
    发明申请
    APPARATUS FOR ACCURATE AND EFFICIENT QUALITY AND RELIABILITY EVALUATION OF MICRO ELECTROMECHANICAL SYSTEMS 失效
    微机电系统精确有效质量和可靠性评估的设备

    公开(公告)号：US20070090902A1

    公开(公告)日：2007-04-26

    申请号：US11163485

    申请日：2005-10-20

    申请人： Hariklia Deligianni ,  Robert Edwards ,  Thomas Fleischman ,  Robert Groves ,  Charles Montrose ,  Richard Volant ,  Ping-Chuan Wang

    发明人： Hariklia Deligianni ,  Robert Edwards ,  Thomas Fleischman ,  Robert Groves ,  Charles Montrose ,  Richard Volant ,  Ping-Chuan Wang

    IPC分类号： H01H51/22

    CPC分类号： H01H59/0009

    摘要： The present invention provides multiple test structures for performing reliability and qualification tests on MEMS switch devices. A Test structure for contact and gap characteristic measurements is employed having a serpentine layout simulates rows of upper and lower actuation electrodes. A cascaded switch chain test is used to monitor process defects with large sample sizes. A ring oscillator is used to measure switch speed and switch lifetime. A resistor ladder test structure is configured having each resistor in series with a switch to be tested, and having each switch-resistor pair electrically connected in parallel. Serial/parallel test structures are proposed with MEMS switches working in tandem with switches of established technology. A shift register is used to monitor the open and close state of the MEMS switches. Pull-in voltage, drop-out voltage, activation leakage current, and switch lifetime measurements are performed using the shift register.

    摘要翻译： 本发明提供用于在MEMS开关装置上执行可靠性和鉴定测试的多个测试结构。 采用具有蛇形布局的接触和间隙特性测量的测试结构来模拟上下驱动电极的行。 级联交换链测试用于监控大样本量的过程缺陷。 环形振荡器用于测量开关速度和开关寿命。 电阻梯形测试结构被配置为具有与要测试的开关串联的每个电阻器，并且每个开关电阻器对并联电连接。 提出了串联/并联测试结构，其中MEMS开关与成熟技术的开关串联工作。 移位寄存器用于监测MEMS开关的开启和关闭状态。 使用移位寄存器执行拉入电压，掉电电压，启动漏电流和开关寿命测量。

    Thermally controlled refractory metal resistor
    6.
    发明授权
    Thermally controlled refractory metal resistor 有权
    耐热耐火金属电阻

    公开(公告)号：US08592947B2

    公开(公告)日：2013-11-26

    申请号：US12962722

    申请日：2010-12-08

    申请人： Joseph M. Lukaitis ,  Deborah M. Massey ,  Timothy D. Sullivan ,  Ping-Chuan Wang ,  Kimball M. Watson

    发明人： Joseph M. Lukaitis ,  Deborah M. Massey ,  Timothy D. Sullivan ,  Ping-Chuan Wang ,  Kimball M. Watson

    IPC分类号： H01L23/36

    CPC分类号： H01L28/20 ,  H01L23/3677 ,  H01L23/5228 ,  H01L27/0211 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A structure and method of fabricating the structure includes a semiconductor substrate having a top surface defining a horizontal direction and a plurality of interconnect levels stacked from a lowermost level proximate the top surface of the semiconductor substrate to an uppermost level furthest from the top surface. Each of the interconnect levels include vertical metal conductors physically connected to one another in a vertical direction perpendicular to the horizontal direction. The vertical conductors in the lowermost level being physically connected to the top surface of the substrate, and the vertical conductors forming a heat sink connected to the semiconductor substrate. A resistor is included in a layer immediately above the uppermost level. The vertical conductors being aligned under a downward vertical resistor footprint of the resistor, and each interconnect level further include horizontal metal conductors positioned in the horizontal direction and being connected to the vertical conductors.

    摘要翻译： 制造该结构的结构和方法包括：半导体衬底，其具有限定水平方向的顶表面和从最接近半导体衬底的顶表面的最底层到距离顶表面最远的最高水平层叠的多个互连层。 每个互连层包括在垂直于水平方向的垂直方向上彼此物理连接的垂直金属导体。 最底层的垂直导体物理地连接到衬底的顶表面，垂直导体形成连接到半导体衬底的散热片。 一个电阻器被包含在最上层的上方的层中。 垂直导体在电阻器的向下垂直电阻器占位面下对准，并且每个互连级别还包括位于水平方向上并且连接到垂直导体的水平金属导体。

    Test structure for locating electromigration voids in dual damascene interconnects
    7.
    发明授权
    Test structure for locating electromigration voids in dual damascene interconnects 失效
    用于定位双镶嵌互连中电迁移空隙的测试结构

    公开(公告)号：US06995392B2

    公开(公告)日：2006-02-07

    申请号：US10214546

    申请日：2002-08-07

    申请人： Paul S. McLaughlin ,  Timothy D. Sullivan ,  Ping-Chuan Wang

    发明人： Paul S. McLaughlin ,  Timothy D. Sullivan ,  Ping-Chuan Wang

    IPC分类号： H01L23/58

    CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A test structure is disclosed for locating electromigration voids in a semiconductor interconnect structure having an interconnect via interconnecting a lower metallization line with an upper metallization line. In an exemplary embodiment, the test structure includes a via portion the top of the interconnect via at the upper metallization line. In addition, a line portion extends from the via portion, wherein the line portion connects to an external probing surface, in addition to a probing surface on the lower metallization line, thereby allowing the identification of any electromigration voids present in the interconnect via.

    摘要翻译： 公开了一种测试结构，用于通过将下部金属化线与上部金属化线相互连接来定位具有互连的半导体互连结构中的电迁移空穴。 在示例性实施例中，测试结构包括在上金属化线处的互连通孔的顶部的通孔部分。 此外，线路部分从通孔部分延伸，其中线部分连接到外部探测表面，以及下部金属化线上的探测表面，从而允许识别互连通孔中存在的任何电迁移空隙。

    THERMALLY CONTROLLED REFRACTORY METAL RESISTOR
    8.
    发明申请
    THERMALLY CONTROLLED REFRACTORY METAL RESISTOR 有权
    热控制的金属电阻器

    公开(公告)号：US20120146186A1

    公开(公告)日：2012-06-14

    申请号：US12962722

    申请日：2010-12-08

    申请人： Joseph M. Lukaitis ,  Deborah M. Massey ,  Timothy D. Sullivan ,  Ping-Chuan Wang ,  Kimball M. Watson

    发明人： Joseph M. Lukaitis ,  Deborah M. Massey ,  Timothy D. Sullivan ,  Ping-Chuan Wang ,  Kimball M. Watson

    IPC分类号： H01L27/06 ,  H01L21/02

    CPC分类号： H01L28/20 ,  H01L23/3677 ,  H01L23/5228 ,  H01L27/0211 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A structure and method of fabricating the structure includes a semiconductor substrate having a top surface defining a horizontal direction and a plurality of interconnect levels stacked from a lowermost level proximate the top surface of the semiconductor substrate to an uppermost level furthest from the top surface. Each of the interconnect levels include vertical metal conductors physically connected to one another in a vertical direction perpendicular to the horizontal direction. The vertical conductors in the lowermost level being physically connected to the top surface of the substrate, and the vertical conductors forming a heat sink connected to the semiconductor substrate. A resistor is included in a layer immediately above the uppermost level. The vertical conductors being aligned under a downward vertical resistor footprint of the resistor, and each interconnect level further include horizontal metal conductors positioned in the horizontal direction and being connected to the vertical conductors.

    摘要翻译： 制造该结构的结构和方法包括：半导体衬底，其具有限定水平方向的顶表面和从最接近半导体衬底的顶表面的最底层到距离顶表面最远的最高水平层叠的多个互连层。 每个互连层包括在垂直于水平方向的垂直方向上彼此物理连接的垂直金属导体。 最底层的垂直导体物理地连接到衬底的顶表面，垂直导体形成连接到半导体衬底的散热片。 一个电阻器被包含在最上层的上方的层中。 垂直导体在电阻器的向下垂直电阻器占位面下对准，并且每个互连级别还包括位于水平方向上并且连接到垂直导体的水平金属导体。

    Test structure for determination of TSV depth
    9.
    发明授权
    Test structure for determination of TSV depth 有权
    用于测定TSV深度的测试结构

    公开(公告)号：US08853693B2

    公开(公告)日：2014-10-07

    申请号：US13423823

    申请日：2012-03-19

    申请人： Hanyi Ding ,  Kai D. Feng ,  Ping-Chuan Wang ,  Zhijian Yang

    发明人： Hanyi Ding ,  Kai D. Feng ,  Ping-Chuan Wang ,  Zhijian Yang

    IPC分类号： H01L21/00 ,  H01L21/768 ,  H01L21/66

    CPC分类号： H01L22/34 ,  H01L21/76898

    摘要： A test structure for a through-silicon-via (TSV) in a semiconductor chip includes a first contact, the first contact being electrically connected to a first TSV; and a second contact, wherein the first contact, second contact, and the first TSV form a first channel, and a depth of the first TSV is determined based on a resistance of the first channel.

    摘要翻译： 半导体芯片中的贯穿硅通孔（TSV）的测试结构包括：第一触点，第一触点电连接到第一TSV; 以及第二触点，其中所述第一触点，所述第二触点和所述第一TSV形成第一通道，并且基于所述第一通道的电阻来确定所述第一TSV的深度。