利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

65 条记录 (耗时 0.031 秒)

    Mirroring data between redundant storage controllers of a storage system
    1.
    发明授权
    Mirroring data between redundant storage controllers of a storage system 有权
    在存储系统的冗余存储控制器之间镜像数据

    公开(公告)号：US08375184B2

    公开(公告)日：2013-02-12

    申请号：US12627440

    申请日：2009-11-30

    申请人： Pankaj Kumar ,  Hang T. Nguyen ,  Mark Yarch ,  Timothy J. Jehl ,  John A. Miller

    发明人： Pankaj Kumar ,  Hang T. Nguyen ,  Mark Yarch ,  Timothy J. Jehl ,  John A. Miller

    IPC分类号： G06F12/00

    CPC分类号： G06F11/2089 ,  G06F11/2097

    摘要： In one embodiment, the present invention includes canisters to control storage of data in a storage system including a plurality of disks. Each of multiple canisters may have a processor configured for uniprocessor mode and having an internal node identifier to identify the processor and an external node identifier to identify another processor with which it is to mirror cached data. The mirroring of cached data may be performed by communication of non-coherent transactions via the PtP interconnect, wherein the PtP interconnect is according to a cache coherent protocol. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，本发明包括用于控制包括多个盘的存储系统中的数据存储的罐。 多个罐中的每一个可以具有配置成用于单处理器模式并具有内部节点标识符以识别处理器和外部节点标识符的处理器，以识别用于镜像缓存数据的另一个处理器。 缓存数据的镜像可以通过经由PtP互连的非相干事务的通信来执行，其中PtP互连是根据高速缓存一致性协议。 描述和要求保护其他实施例。

    Mirroring Data Between Redundant Storage Controllers Of A Storage System
    2.
    发明申请
    Mirroring Data Between Redundant Storage Controllers Of A Storage System 有权
    在存储系统的冗余存储控制器之间镜像数据

    公开(公告)号：US20110131373A1

    公开(公告)日：2011-06-02

    申请号：US12627440

    申请日：2009-11-30

    申请人： Pankaj Kumar ,  Hang T. Nguyen ,  Mark Yarch ,  Timothy J. Jehl ,  John A. Miller

    发明人： Pankaj Kumar ,  Hang T. Nguyen ,  Mark Yarch ,  Timothy J. Jehl ,  John A. Miller

    IPC分类号： G06F12/08 ,  G06F12/00 ,  G06F12/16

    CPC分类号： G06F11/2089 ,  G06F11/2097

    摘要： In one embodiment, the present invention includes canisters to control storage of data in a storage system including a plurality of disks. Each of multiple canisters may have a processor configured for uniprocessor mode and having an internal node identifier to identify the processor and an external node identifier to identify another processor with which it is to mirror cached data. The mirroring of cached data may be performed by communication of non-coherent transactions via the PtP interconnect, wherein the PtP interconnect is according to a cache coherent protocol. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，本发明包括用于控制包括多个盘的存储系统中的数据存储的罐。 多个罐中的每一个可以具有配置成用于单处理器模式并具有内部节点标识符以识别处理器和外部节点标识符的处理器，以识别用于镜像缓存数据的另一个处理器。 缓存数据的镜像可以通过经由PtP互连的非相干事务的通信来执行，其中PtP互连是根据高速缓存一致性协议。 描述和要求保护其他实施例。

    Processing out of order transactions for mirrored subsystems using a cache to track write operations
    3.
    发明授权
    Processing out of order transactions for mirrored subsystems using a cache to track write operations 有权
    处理使用高速缓存跟踪写入操作的镜像子系统的顺序事务

    公开(公告)号：US08909862B2

    公开(公告)日：2014-12-09

    申请号：US12495676

    申请日：2009-06-30

    申请人： Mark A. Yarch ,  Pankaj Kumar ,  Hang T. Nguyen

    发明人： Mark A. Yarch ,  Pankaj Kumar ,  Hang T. Nguyen

    IPC分类号： G06F12/08 ,  G06F11/16 ,  G06F11/20

    CPC分类号： G06F11/1666 ,  G06F11/20 ,  G06F2201/82

    摘要： Methods and apparatus relating to processing out of order transactions for mirrored subsystems. A first device (that is mirroring data from a second device) includes a cache to track out of order write operations prior to writing data from the write operations to memory. A register may be used to track the state of the cache in response to receipt of a special transaction, which may be a posted transaction or snapshot. The first devise transmits an acknowledgement of commitment of the data to memory once all cache entries, as recorded at a select point by the register, are emptied or otherwise invalidated. Devices may communicate via a peripheral component interconnect express (PCIe) interconnect, and may include a point-to-point or serial link. Various components may be on the same integrated circuit die. An uninterrupted power supply or batteries may supply power in response to a power failure.

    摘要翻译： 涉及处理镜像子系统的乱序事务的方法和装置。 第一设备（即来自第二设备的镜像数据）包括在从写入操作到存储器的数据写入之前跟踪故障写入操作的高速缓存。 可以使用寄存器来跟踪高速缓存的状态以响应特殊事务的接收，这可以是已发布的事务或快照。 一旦在寄存器的选择点处记录的所有缓存条目被清空或以其他方式被无效，则第一设备将数据承诺的确认传送到存储器。 设备可以通过外围组件互连快速（PCIe）互连进行通信，并且可以包括点到点或串行链路。 各种组件可以在相同的集成电路管芯上。 不间断的电源或电池可能会供电以响应电源故障。

    PROCESSING OUT OF ORDER TRANSACTIONS FOR MIRRORED SUBSYSTEMS
    5.
    发明申请
    PROCESSING OUT OF ORDER TRANSACTIONS FOR MIRRORED SUBSYSTEMS 有权
    处理用于镜像子系统的订单交易

    公开(公告)号：US20100332756A1

    公开(公告)日：2010-12-30

    申请号：US12495676

    申请日：2009-06-30

    申请人： Mark A. Yarch ,  Pankaj Kumar ,  Hang T. Nguyen

    发明人： Mark A. Yarch ,  Pankaj Kumar ,  Hang T. Nguyen

    IPC分类号： G06F12/08 ,  G06F1/30

    CPC分类号： G06F11/1666 ,  G06F11/20 ,  G06F2201/82

    摘要： Methods and apparatus relating to processing out of order transactions for mirrored subsystems are described. In one embodiment, a device (that is mirroring data from another device) includes a cache to track out of order write operations prior to writing the data from the write operations to memory. A register may be used to track the state of the cache and cause acknowledgement of commitment of the data to memory once all cache entries, as recorded at a select point by the register, are emptied or otherwise invalidated. Other embodiments are also disclosed.

    摘要翻译： 描述与处理镜像子系统的乱序事务相关的方法和装置。 在一个实施例中，在将写入操作的数据写入存储器之前，设备（即来自另一个设备的数据镜像）包括高速缓存以跟踪不合格的写入操作。 一旦由寄存器在选择点记录的所有高速缓存条目被清空或以其它方式被无效，则可以使用寄存器来跟踪高速缓存的状态并导致将数据承诺的确认。 还公开了其他实施例。

    Voltage level translator circuit for reducing jitter
    8.
    发明授权
    Voltage level translator circuit for reducing jitter 有权
    用于降低抖动的电压电平转换器电路

    公开(公告)号：US08427223B2

    公开(公告)日：2013-04-23

    申请号：US13186310

    申请日：2011-07-19

    申请人： Pankaj Kumar ,  Pramod Parameswaran ,  Makeshwar Kothandaraman

    发明人： Pankaj Kumar ,  Pramod Parameswaran ,  Makeshwar Kothandaraman

    IPC分类号： H03L5/00

    CPC分类号： H03K3/356113

    摘要： A voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply includes an input stage for receiving the input signal, the input stage including at least first and second nodes, a voltage at the second node being a logical complement of a voltage at the first node. A load circuit is coupled with the input stage, the load circuit being operative to at least temporarily store a signal at the first and/or second nodes which is indicative of a logical state of the input signal. An output stage connected with the second node is operative to generate an output signal which is indicative of a logical state of the input signal. The voltage level translator circuit further includes a compensation circuit connected with the output stage and operative to balance pull-up and pull-down propagation delays in the voltage level translator circuit as a function of a voltage at the first node.

    摘要翻译： 用于将参考第一电压源的输入信号转换为参考第二电压源的输出信号的电压电平转换器电路包括用于接收输入信号的输入级，输入级至少包括第一和第二节点， 第二节点是第一节点处的电压的逻辑补码。 负载电路与输入级耦合，负载电路可操作以至少临时存储指示输入信号的逻辑状态的第一和/或第二节点处的信号。 与第二节点连接的输出级可操作以产生指示输入信号的逻辑状态的输出信号。 电压电平转换器电路还包括与输出级连接的补偿电路，并且可操作以平衡电压电平转换器电路中的上拉和下拉传播延迟作为第一节点处的电压的函数。

    Impedance Mismatch Detection Circuit
    9.
    发明申请
    Impedance Mismatch Detection Circuit 有权
    阻抗不匹配检测电路

    公开(公告)号：US20130002267A1

    公开(公告)日：2013-01-03

    申请号：US13171725

    申请日：2011-06-29

    申请人： Makeshwar Kothandaraman ,  Pankaj Kumar ,  Pramod Parameswaran

    发明人： Makeshwar Kothandaraman ,  Pankaj Kumar ,  Pramod Parameswaran

    IPC分类号： G01R27/28

    CPC分类号： H03F3/45475 ,  H03F2203/45594

    摘要： A comparison circuit for detecting impedance mismatch between pull-up and pull-down devices in a circuit to be monitored includes a comparator operative to receive first and second signals and to generate, as an output, a third signal indicative of a difference between the first and second signals. A first signal generator is operative to generate the first signal indicative of a difference between reference pull-up and pull-down currents that is scaled by a prescribed amount. The reference pull-up current is indicative of a current flowing through at least one corresponding pull-up transistor device in the circuit to be monitored. The pull-down reference current is indicative of a current flowing through at least one corresponding pull-down transistor device in the circuit to be monitored. A second signal generator connected with the second input of the comparator is operative to generate the second signal as a reference voltage defining a prescribed impedance mismatch threshold associated with the circuit to be monitored.

    摘要翻译： 用于检测待监测电路中的上拉和下拉器件之间的阻抗失配的比较电路包括一个比较器，用于接收第一和第二信号，并产生一个第三信号，该第三信号指示第一和第二信号之间的差值 和第二信号。 第一信号发生器用于产生表示参考上拉和下拉电流之间的差的第一信号，该下拉电流被缩放规定量。 参考上拉电流指示流过待监测电路中的至少一个对应的上拉晶体管器件的电流。 下拉参考电流表示流过待监测电路中的至少一个对应的下拉晶体管器件的电流。 与比较器的第二输入端连接的第二信号发生器可操作以产生第二信号作为参考电压，该参考电压限定与待监视电路相关联的规定阻抗失配阈值。