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公开(公告)号：US09230636B2
公开(公告)日：2016-01-05
申请号：US14137808
申请日：2013-12-20
申请人： Pascal A. Meinerzhagen , Jaydeep P. Kulkarni , Muhammad M. Khellah , Cyrille Dray , Dinesh Somasekhar , James W. Tschanz , Vivek K. De
发明人： Pascal A. Meinerzhagen , Jaydeep P. Kulkarni , Muhammad M. Khellah , Cyrille Dray , Dinesh Somasekhar , James W. Tschanz , Vivek K. De
IPC分类号： G11C5/14 , G11C11/4074 , G11C11/16 , G11C16/06 , G11C11/406 , G11C11/4076 , G11C5/06 , G11C11/408
CPC分类号： G11C11/4074 , G11C5/063 , G11C5/14 , G11C5/145 , G11C5/148 , G11C11/1697 , G11C11/406 , G11C11/4076 , G11C11/4085 , G11C11/4087 , G11C11/417 , G11C16/06
摘要： Described is an apparatus which comprises: a first power supply node to provide a first power supply, a second power supply node, and a third power supply node; a first transistor which is operable to couple the first and second power supply nodes; and a charge pump circuit to provide a boosted voltage to the third power supply node in one mode, and to recover charge from the second power node in another mode. Described is a memory unit which comprises: a DRAM which is operable to be refreshed; a gated power supply node coupled to the DRAM to provide a gated power supply to the DRAM; and a charge recycling circuit to recover charge from the gated power supply node after the DRAM is refreshed.
摘要翻译： 描述了一种装置，包括：提供第一电源的第一电源节点，第二电源节点和第三电源节点; 第一晶体管，其可操作以耦合所述第一和第二电源节点; 以及电荷泵电路，以一种模式向第三电源节点提供升压电压，并且在另一模式下从第二功率节点恢复电荷。 描述了一种存储单元，其包括：可操作以刷新的DRAM; 门极电源节点，其耦合到DRAM以向DRAM提供门控电源; 以及充电回收电路，用于在DRAM被刷新之后从门控电源节点恢复电荷。
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公开(公告)号：US09153304B2
公开(公告)日：2015-10-06
申请号：US13536521
申请日：2012-06-28
申请人： Jaydeep P. Kulkarni , Muhammad M. Khellah , James W. Tschanz , Bibiche M. Geuskens , Vivek K. De
发明人： Jaydeep P. Kulkarni , Muhammad M. Khellah , James W. Tschanz , Bibiche M. Geuskens , Vivek K. De
IPC分类号： G11C11/00 , G11C7/22 , G11C11/419 , G11C11/412 , G11C11/413
CPC分类号： G11C11/419 , G11C7/227 , G11C11/412 , G11C11/413
摘要： Described is an apparatus for self-induced reduction in write minimum supply voltage for a memory element. The apparatus comprises: a memory element having cross-coupled inverters coupled to a first supply node; a power device coupled to the first supply node and a second supply node, the second supply node coupled to power supply; and an access device having a gate terminal coupled to a word-line, a first terminal coupled to the memory element, and a second terminal coupled to a bit-line which is operable to be pre-discharged to a logical low level prior to write operation.
摘要翻译： 描述了一种用于存储元件的写入最小电源电压的自感应降低的装置。 该装置包括：具有耦合到第一电源节点的交叉耦合的反相器的存储元件; 耦合到第一电源节点和第二电源节点的电源设备，第二电源节点耦合到电源; 以及具有耦合到字线的栅极端子，耦合到存储器元件的第一端子和耦合到位线的第二端子的存取装置，该位线可操作以在写入之前预放电到逻辑低电平 操作。
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公开(公告)号：US20140003132A1
公开(公告)日：2014-01-02
申请号：US13536521
申请日：2012-06-28
申请人： Jaydeep P. Kulkarni , Muhammad M Khellah , James W. Tschanz , Bibiche M. Geuskens , Vivek K. De
发明人： Jaydeep P. Kulkarni , Muhammad M Khellah , James W. Tschanz , Bibiche M. Geuskens , Vivek K. De
CPC分类号： G11C11/419 , G11C7/227 , G11C11/412 , G11C11/413
摘要： Described is an apparatus for self-induced reduction in write minimum supply voltage for a memory element. The apparatus comprises: a memory element having cross-coupled inverters coupled to a first supply node; a power device coupled to the first supply node and a second supply node, the second supply node coupled to power supply; and an access device having a gate terminal coupled to a word-line, a first terminal coupled to the memory element, and a second terminal coupled to a bit-line which is operable to be pre-discharged to a logical low level prior to write operation.
摘要翻译： 描述了一种用于存储元件的写入最小电源电压的自感应降低的装置。 该装置包括：具有耦合到第一电源节点的交叉耦合的反相器的存储元件; 耦合到第一电源节点和第二电源节点的电源设备，第二电源节点耦合到电源; 以及具有耦合到字线的栅极端子，耦合到存储器元件的第一端子和耦合到位线的第二端子的存取装置，该位线可操作以在写入之前预放电到逻辑低电平 操作。
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公开(公告)号：US20130003469A1
公开(公告)日：2013-01-03
申请号：US13174352
申请日：2011-06-30
IPC分类号： G11C7/00
CPC分类号： G11C7/02 , G11C11/419
摘要： Embodiments for data dependent boosted (DDB) bit cells that may allow for smaller minimum cell supplies (Vmin) without necessarily having to increase device dimensions are presented.
摘要翻译： 呈现可能允许更小的最小电池电源（Vmin）的数据相关升压（DDB）位单元的实施例，而不必增加器件尺寸。
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公开(公告)号：US08488390B2
公开(公告)日：2013-07-16
申请号：US13174352
申请日：2011-06-30
IPC分类号： G11C7/00
CPC分类号： G11C7/02 , G11C11/419
摘要： Embodiments for data dependent boosted (DDB) bit cells that may allow for smaller minimum cell supplies (Vmin) without necessarily having to increase device dimensions are presented.
摘要翻译： 呈现可能允许更小的最小电池电源（Vmin）的数据相关升压（DDB）位单元的实施例，而不必增加器件尺寸。
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6.发明申请METHODS AND SYSTEMS TO SELECTIVELY BOOST AN OPERATING VOLTAGE OF, AND CONTROLS TO AN 8T BIT-CELL ARRAY AND/OR OTHER LOGIC BLOCKS 有权选择性地增加对8T位单元阵列和/或其他逻辑块的操作电压和控制的方法和系统公开(公告)号：US20150009751A1
公开(公告)日：2015-01-08
申请号：US14350546
申请日：2012-03-26
IPC分类号： G11C5/14 , G11C7/12 , G11C11/418 , G11C8/10 , G11C11/419
CPC分类号： G11C11/419 , G11C5/14 , G11C5/145 , G11C5/147 , G11C5/148 , G11C7/12 , G11C8/08 , G11C8/10 , G11C11/4074 , G11C11/412 , G11C11/417 , G11C11/418 , G11C13/0038 , G11C29/021 , G11C29/028 , G11C2207/2227
摘要： Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin and/or improve energy efficiency in the single-Vcc environment. The logic block may include bit cells of a register file, a low-level processor cache, and/or other memory system. A cell Vcc may be boosted during a read mode and/or write wordlines (WWLs) and/or read wordlines (RWLs) may be asserted with boost. A wordline decoder may include a voltage level shifter with differential split-level logic, and a dynamic NAND, which may include NAND logic, a keeper circuit, and logic to delay a keeper control based on a delay of the level shifter to reduce contention during an initial NAND evaluation phase.
摘要翻译： 提供多Vcc环境的方法和系统，例如选择性地提高逻辑块的工作电压和/或向逻辑块提供电平移位控制。 可以实现多Vcc环境以将Vmin限制逻辑块与单Vcc环境隔离，例如在单Vcc环境中减少Vmin和/或提高能量效率。 逻辑块可以包括寄存器文件的位单元，低级处理器高速缓存和/或其他存储器系统。 可以在读取模式期间升高单元Vcc，和/或写入字线（WWL）和/或读取字线（RWL）可以通过升压来断言。 字线解码器可以包括具有差分分离级逻辑的电压电平移位器和动态NAND，其可以包括NAND逻辑，保持器电路和用于基于电平转换器的延迟来延迟保持器控制的逻辑，以减少在 初始NAND评估阶段。
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7.发明授权Methods and systems to selectively boost an operating voltage of, and controls to an 8T bit-cell array and/or other logic blocks 有权选择性地提高8T位单元阵列和/或其他逻辑块的工作电压并控制其的方法和系统公开(公告)号：US09299395B2
公开(公告)日：2016-03-29
申请号：US14350546
申请日：2012-03-26
IPC分类号： G11C11/419 , G11C5/14 , G11C7/08 , G11C11/4074 , G11C11/417 , G11C7/12 , G11C8/10 , G11C11/418 , G11C13/00 , G11C29/02 , G11C11/412
CPC分类号： G11C11/419 , G11C5/14 , G11C5/145 , G11C5/147 , G11C5/148 , G11C7/12 , G11C8/08 , G11C8/10 , G11C11/4074 , G11C11/412 , G11C11/417 , G11C11/418 , G11C13/0038 , G11C29/021 , G11C29/028 , G11C2207/2227
摘要： Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin and/or improve energy efficiency in the single-Vcc environment. The logic block may include bit cells of a register file, a low-level processor cache, and/or other memory system. A cell Vcc may be boosted during a read mode and/or write wordlines (WWLs) and/or read wordlines (RWLs) may be asserted with boost. A wordline decoder may include a voltage level shifter with differential split-level logic, and a dynamic NAND, which may include NAND logic, a keeper circuit, and logic to delay a keeper control based on a delay of the level shifter to reduce contention during an initial NAND evaluation phase.
摘要翻译： 提供多Vcc环境的方法和系统，例如选择性地提高逻辑块的工作电压和/或向逻辑块提供电平移位控制。 可以实现多Vcc环境以将Vmin限制逻辑块与单Vcc环境隔离，例如在单Vcc环境中减少Vmin和/或提高能量效率。 逻辑块可以包括寄存器文件的位单元，低级处理器高速缓存和/或其他存储器系统。 可以在读取模式期间升高单元Vcc，和/或写入字线（WWL）和/或读取字线（RWL）可以通过升压来断言。 字线解码器可以包括具有差分分离级逻辑的电压电平移位器和动态NAND，其可以包括NAND逻辑，保持器电路和用于基于电平移位器的延迟来延迟保持器控制的逻辑，以减少在 初始NAND评估阶段。
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公开(公告)号：US08467263B2
公开(公告)日：2013-06-18
申请号：US12823642
申请日：2010-06-25
申请人： Jaydeep P. Kulkarni , Muhammad M. Khellah , Bibiche M. Geuskens , Arijit Raychowdhury , Tanay Karnik , Vivek K. De
发明人： Jaydeep P. Kulkarni , Muhammad M. Khellah , Bibiche M. Geuskens , Arijit Raychowdhury , Tanay Karnik , Vivek K. De
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C7/12 , G11C7/20 , G11C11/412 , G11C11/413
摘要： In some embodiments, write wordline boost may be obtained from wordline driver boost and/or from bit line access transistor boost.
摘要翻译： 在一些实施例中，可以从字线驱动器升压和/或来自位线存取晶体管升压获得写入字线升压。
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9.发明申请RESILIENT REGISTER FILE CIRCUIT FOR DYNAMIC VARIATION TOLERANCE AND METHOD OF OPERATING THE SAME 有权用于动态变化公差的弹性寄存器文件电路及其操作方法公开(公告)号：US20140032980A1
公开(公告)日：2014-01-30
申请号：US13976859
申请日：2011-12-28
IPC分类号： G06F11/07
CPC分类号： G06F11/1068 , G06F9/30141 , G06F9/3861 , G06F11/0751 , G06F11/1008 , G11C7/18 , G11C29/42 , G11C29/52
摘要： The disclosed system and method detect and correct register file read path errors that may occur as a result of reducing or eliminating supply voltage guardbands and/or frequency guardbands for a CPU, thereby increasing overall energy efficiency of the system.
摘要翻译： 所公开的系统和方法检测并校正由于减少或消除CPU的电源电压保护带和/或频率保护带而可能发生的寄存器文件读取路径错误，从而提高了系统的总体能量效率。
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10.发明授权Resilient register file circuit for dynamic variation tolerance and method of operating the same 有权用于动态变化公差的弹性寄存器文件电路及其操作方法公开(公告)号：US09329918B2
公开(公告)日：2016-05-03
申请号：US13976859
申请日：2011-12-28
CPC分类号： G06F11/1068 , G06F9/30141 , G06F9/3861 , G06F11/0751 , G06F11/1008 , G11C7/18 , G11C29/42 , G11C29/52
摘要： The disclosed system and method detect and correct register file read path errors that may occur as a result of reducing or eliminating supply voltage guardbands and/or frequency guardbands for a CPU, thereby increasing overall energy efficiency of the system.
摘要翻译： 所公开的系统和方法检测并校正由于减少或消除CPU的电源电压保护带和/或频率保护带而可能发生的寄存器文件读取路径错误，从而提高系统的总体能量效率。
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