公开(公告)号：US08263497B2

公开(公告)日：2012-09-11

申请号：US12352718

申请日：2009-01-13

申请人： Paul S. Andry ,  John M. Cotte ,  Michael F. Lofaro ,  Edmund J. Sprogis ,  James A. Tornello ,  Cornelia K. Tsang

发明人： Paul S. Andry ,  John M. Cotte ,  Michael F. Lofaro ,  Edmund J. Sprogis ,  James A. Tornello ,  Cornelia K. Tsang

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05184 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

摘要： An assembly including a main wafer having a body with a front side and a back side and a plurality of blind electrical vias terminating above the back side, and a handler wafer, is obtained. A step includes exposing the blind electrical vias to various heights on the back side. Another step involves applying a first chemical mechanical polish process to the back side, to open any of the surrounding insulator adjacent the end regions of the cores remaining after the exposing step, and to co-planarize the via conductive cores, the surrounding insulator adjacent the side regions of the cores, and the body of the main wafer. Further steps include etching the back side to produce a uniform standoff height of each of the vias across the back side; depositing a dielectric across the back side; and applying a second chemical mechanical polish process to the back side.

摘要翻译： 获得包括具有前侧和后侧的主体的主晶片和终止于背面的多个盲电通路的组件和处理器晶片。 一个步骤包括将盲电通孔暴露在背面的各种高度上。 另一个步骤涉及将第一化学机械抛光工艺应用于背面，以便打开暴露步骤之后残留的芯的端部附近的任何周围的绝缘体，并且将通孔导电芯，邻近的绝缘体 芯的侧面区域和主晶片的主体。 进一步的步骤包括蚀刻背面以产生穿过背面的每个通路的均匀间隔高度; 在背面沉积电介质; 并向后侧施加第二化学机械抛光工艺。

公开(公告)号：US20100178766A1

公开(公告)日：2010-07-15

申请号：US12352718

申请日：2009-01-13

申请人： Paul S. Andry ,  John M. Cotte ,  Michael F. Lofaro ,  Edmund J. Sprogis ,  James A. Tornello ,  Cornelia K. Tsang

发明人： Paul S. Andry ,  John M. Cotte ,  Michael F. Lofaro ,  Edmund J. Sprogis ,  James A. Tornello ,  Cornelia K. Tsang

IPC分类号： H01L21/461

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05184 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

摘要： An assembly including a main wafer having a body with a front side and a back side, and a handler wafer, is obtained. The main wafer has a plurality of blind electrical vias terminating above the back side. The blind electrical vias have conductive cores with surrounding insulator adjacent side and end regions of the cores. The handler wafer is secured to the front side of the body of the main wafer. An additional step includes exposing the blind electrical vias on the back side. The blind electrical vias are exposed to various heights across the back side. Another step involves applying a first chemical mechanical polish process to the back side, to open any of the surrounding insulator adjacent the end regions of the cores remaining after the exposing step, and to co-planarize the via conductive cores, the surrounding insulator adjacent the side regions of the cores, and the body of the main wafer. Further steps include etching the back side to produce a uniform standoff height of each of the vias across the back side; depositing a dielectric across the back side; and applying a second chemical mechanical polish process to the back side, to open the dielectric only adjacent the conductive cores of the vias.

摘要翻译： 获得包括具有前侧和后侧的主体的主晶片和处理器晶片的组件。 主晶片具有在背面上方终止的多个盲电通路。 盲电通孔具有导电芯，其周围绝缘体邻近芯的侧面和端部区域。 处理器晶片固定到主晶片的主体的前侧。 另外的步骤包括在背面暴露盲电通孔。 盲孔通过背面暴露于各种高度。 另一个步骤涉及将第一化学机械抛光工艺应用于背面，以便打开暴露步骤之后残留的芯的端部附近的任何周围的绝缘体，并且将通孔导电芯，邻近的绝缘体 芯的侧面区域和主晶片的主体。 进一步的步骤包括蚀刻背面以产生穿过背面的每个通路的均匀间隔高度; 在背面沉积电介质; 以及向后侧施加第二化学机械抛光工艺，以仅在通孔的导电芯附近打开电介质。

公开(公告)号：US07955160B2

公开(公告)日：2011-06-07

申请号：US12135315

申请日：2008-06-09

申请人： Michael A. Cobb ,  Dinesh R. Koli ,  Michael F. Lofaro ,  Dennis G. Manzer ,  Paraneetha Poloju ,  James A. Tornello

发明人： Michael A. Cobb ,  Dinesh R. Koli ,  Michael F. Lofaro ,  Dennis G. Manzer ,  Paraneetha Poloju ,  James A. Tornello

IPC分类号： B24B1/00

CPC分类号： B24B37/042 ,  B24B37/11

摘要： A glass mold polishing structure and method. The method includes providing a polishing tool comprising mounting plate, a chuck plate over and mechanically attached to the mounting plate, and a pad structure over and mechanically attached to the chuck plate. A retaining structure is attached the chuck plate. A glass mold comprising a plurality of cavities is placed on the pad structure and within a perimeter formed by the retaining structure. A vacuum device is attached to the chuck plate. The vacuum device is activated such that a vacuum is formed and mechanically attaches the glass mold to the pad structure. The polishing tool comprising the glass mold mechanically attached to the pad structure is placed over and in contact with the polishing pad. The polishing tool comprising the glass mold is rotated. The glass mold is polished as a result of the rotation.

摘要翻译： 玻璃模具抛光结构及方法。 该方法包括提供一种抛光工具，该抛光工具包括安装板，卡盘板，并且机械地连接到安装板上，以及衬垫结构，并且在机械上附接到卡盘板上。 保持结构安装在卡盘板上。 包括多个空腔的玻璃模具被放置在垫结构上并且在由保持结构形成的周边内。 真空装置安装在卡板上。 激活真空装置，使得形成真空并将玻璃模具机械地附接到衬垫结构。 包括机械地附接到垫结构的玻璃模具的抛光工具放置在抛光垫上并与抛光垫接触。 包括玻璃模具的抛光工具旋转。 玻璃模具由于旋转而被抛光。

公开(公告)号：US20090305616A1

公开(公告)日：2009-12-10

申请号：US12135315

申请日：2008-06-09

申请人： Michael A. Cobb ,  Dinesh R. Koli ,  Michael F. Lofaro ,  Dennis G. Manzer ,  Praneetha Poloju ,  James A. Tornello

发明人： Michael A. Cobb ,  Dinesh R. Koli ,  Michael F. Lofaro ,  Dennis G. Manzer ,  Praneetha Poloju ,  James A. Tornello

IPC分类号： B24B7/10

CPC分类号： B24B37/042 ,  B24B37/11

摘要： A glass mold polishing structure and method. The method includes providing a polishing tool comprising mounting plate, a chuck plate over and mechanically attached to the mounting plate, and a pad structure over and mechanically attached to the chuck plate. A retaining structure is attached the chuck plate. A glass mold comprising a plurality of cavities is placed on the pad structure and within a perimeter formed by the retaining structure. A vacuum device is attached to the chuck plate. The vacuum device is activated such that a vacuum is formed and mechanically attaches the glass mold to the pad structure. The polishing tool comprising the glass mold mechanically attached to the pad structure is placed over and in contact with the polishing pad. The polishing tool comprising the glass mold is rotated. The glass mold is polished as a result of the rotation.

摘要翻译： 玻璃模具抛光结构及方法。 该方法包括提供一种抛光工具，该抛光工具包括安装板，卡盘板，并且机械地连接到安装板上，以及衬垫结构，并且在机械上附接到卡盘板上。 保持结构安装在卡盘板上。 包括多个空腔的玻璃模具被放置在垫结构上并且在由保持结构形成的周边内。 真空装置安装在卡板上。 激活真空装置，使得形成真空并将玻璃模具机械地附接到衬垫结构。 包括机械地附接到垫结构的玻璃模具的抛光工具放置在抛光垫上并与抛光垫接触。 包括玻璃模具的抛光工具旋转。 玻璃模具由于旋转而被抛光。

公开(公告)号：US08524606B2

公开(公告)日：2013-09-03

申请号：US13012821

申请日：2011-01-25

申请人： Leslie Charns ,  John M. Cotte ,  Jason E. Cummings ,  Lukasz J. Hupka ,  Dinesh R. Koli ,  Tomohisa Konno ,  Mahadevaiyer Krishnan ,  Michael F. Lofaro ,  Jakub W. Nalaskowski ,  Masahiro Noda ,  Dinesh K. Penigalapati ,  Tatsuya Yamanaka

发明人： Leslie Charns ,  John M. Cotte ,  Jason E. Cummings ,  Lukasz J. Hupka ,  Dinesh R. Koli ,  Tomohisa Konno ,  Mahadevaiyer Krishnan ,  Michael F. Lofaro ,  Jakub W. Nalaskowski ,  Masahiro Noda ,  Dinesh K. Penigalapati ,  Tatsuya Yamanaka

IPC分类号： H01L21/311

CPC分类号： H01L21/31053 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545

摘要： Planarization methods include depositing a mask material on top of an overburden layer on a semiconductor wafer. The mask material is planarized to remove the mask material from up areas of the overburden layer to expose the overburden layer without removing the mask material from down areas. The exposed overburden layer is wet etched and leaves a thickness remaining over an underlying layer. Remaining portions of the mask layer and the exposed portions of the overburden layer are planarized to expose the underlying layer.

摘要翻译： 平面化方法包括在半导体晶片上的覆盖层顶部沉积掩模材料。 将掩模材料平坦化以从覆盖层的上部区域去除掩模材料，以暴露覆盖层，而不从掩模材料向下区域移除。 暴露的覆盖层被湿蚀刻并留下厚度保留在下层上。 掩模层的剩余部分和覆盖层的暴露部分被平坦化以暴露下面的层。

公开(公告)号：US08513127B2

公开(公告)日：2013-08-20

申请号：US13012836

申请日：2011-01-25

申请人： Josephine B. Chang ,  Leslie Charns ,  Jason E. Cummings ,  Michael A. Guillorn ,  Lukasz J. Hupka ,  Dinesh R. Koli ,  Tomohisa Konno ,  Mahadevaiyer Krishnan ,  Michael F. Lofaro ,  Jakub W. Nalaskowski ,  Masahiro Noda ,  Dinesh K. Penigalapati ,  Tatsuya Yamanaka

发明人： Josephine B. Chang ,  Leslie Charns ,  Jason E. Cummings ,  Michael A. Guillorn ,  Lukasz J. Hupka ,  Dinesh R. Koli ,  Tomohisa Konno ,  Mahadevaiyer Krishnan ,  Michael F. Lofaro ,  Jakub W. Nalaskowski ,  Masahiro Noda ,  Dinesh K. Penigalapati ,  Tatsuya Yamanaka

IPC分类号： H01L21/302

CPC分类号： H01L21/31053 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545

摘要： A planarization method includes planarizing a semiconductor wafer in a first chemical mechanical polish step to remove overburden and planarize a top layer leaving a thickness of top layer material over underlying layers. The top layer material is planarized in a second chemical mechanical polish step to further remove the top layer and expose underlying layers of a second material and a third material such that a selectivity of the top layer material to the second material to the third material is between about 1:1:1 to about 2:1:1 to provide a planar topography.

摘要翻译： 平面化方法包括在第一化学机械抛光步骤中平坦化半导体晶片以去除覆盖层并平坦化顶层，从而在顶层之上留下厚度的顶层材料。 顶层材料在第二化学机械抛光步骤中被平坦化，以进一步去除顶层并暴露第二材料和第三材料的下层，使得顶层材料对第二材料对第三材料的选择性在 约1：1至约2：1：1，以提供平面形貌。

公开(公告)号：US08273598B2

公开(公告)日：2012-09-25

申请号：US13020051

申请日：2011-02-03

申请人： Matthew J. Breitwisch ,  Chieh-Fang Chen ,  Shih-Hung Chen ,  Eric A. Joseph ,  Chung Hon Lam ,  Michael F. Lofaro ,  Hsiang-Lan Lung ,  Alejandro G. Schrott ,  Min Yang

发明人： Matthew J. Breitwisch ,  Chieh-Fang Chen ,  Shih-Hung Chen ,  Eric A. Joseph ,  Chung Hon Lam ,  Michael F. Lofaro ,  Hsiang-Lan Lung ,  Alejandro G. Schrott ,  Min Yang

IPC分类号： H01L21/00

CPC分类号： H01L45/06 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1683

摘要： A method of forming bit line aligned to a phase change material that includes forming a pedestal of a sacrificial material on a portion of a lower electrode and forming at least one dielectric material adjacent to the sacrificial material, wherein the at least one dielectric material has an upper surface substantially coplanar with an upper surface of the pedestal of the sacrificial material. The pedestal of the sacrificial material is removed selective to the at least one dielectric material and the lower electrode to provide an opening to an exposed surface of the lower electrode. A phase change material is formed on the exposed surface of the lower electrode, and the opening is filled with a conductive fill material. A self-aligned etch back process is also provided.

摘要翻译： 一种形成与相变材料对准的位线的方法，包括在下电极的一部分上形成牺牲材料的基座并且形成与所述牺牲材料相邻的至少一个电介质材料，其中所述至少一种电介质材料具有 上表面与牺牲材料的基座的上表面基本共面。 牺牲材料的基座被选择性地移除到至少一个电介质材料和下电极以提供到下电极的暴露表面的开口。 在下电极的暴露表面上形成相变材料，并且用导电填充材料填充开口。 还提供了自对准的回蚀工艺。

公开(公告)号：US20120083121A1

公开(公告)日：2012-04-05

申请号：US13012879

申请日：2011-01-25

申请人： Takashi Ando ,  Leslie Charns ,  Jason E. Cummings ,  Lukasz J. Hupka ,  Dinesh R. Koli ,  Tomohisa Konno ,  Mahadevaiyer Krishnan ,  Michael F. Lofaro ,  Jakub W. Nalaskowski ,  Masahiro Noda ,  Dinesh K. Penigalapati ,  Tatsuya Yamanaka

发明人： Takashi Ando ,  Leslie Charns ,  Jason E. Cummings ,  Lukasz J. Hupka ,  Dinesh R. Koli ,  Tomohisa Konno ,  Mahadevaiyer Krishnan ,  Michael F. Lofaro ,  Jakub W. Nalaskowski ,  Masahiro Noda ,  Dinesh K. Penigalapati ,  Tatsuya Yamanaka

IPC分类号： H01L21/463

CPC分类号： H01L21/31053 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545

摘要： Methods for polishing multiple dielectric layers to form replacement metal gate structures include a first chemical mechanical polish step to remove overburden and planarize a top layer to leave a planarized thickness over a gate structure. A second chemical mechanical polish step includes removal of the thickness to expose an underlying covered surface of a dielectric of the gate structure with a slurry configured to polish the top layer and the underlying covered surface substantially equally to accomplish a planar topography. A third chemical mechanical polish step is employed to remove the dielectric of the gate structure and expose a gate conductor.

摘要翻译： 用于抛光多个电介质层以形成替换金属栅极结构的方法包括第一化学机械抛光步骤，以去除覆盖层并平坦化顶层以在栅极结构上留下平坦化的厚度。 第二化学机械抛光步骤包括去除厚度以暴露栅极结构的电介质的下面覆盖的表面，其中浆料被配置成基本上等同地抛光顶层和下面的被覆表面以实现平面形貌。 采用第三种化学机械抛光步骤来去除栅极结构的电介质并露出栅极导体。

公开(公告)号：US07179760B2

公开(公告)日：2007-02-20

申请号：US10908833

申请日：2005-05-27

申请人： Richard A. Conti ,  Thomas F. Houghton ,  Michael F. Lofaro ,  Jeffery B. Maxson ,  Ann H. McDonald ,  Yun-Yu Wang ,  Keith Kwong Hon Wong ,  Daewon Yang

发明人： Richard A. Conti ,  Thomas F. Houghton ,  Michael F. Lofaro ,  Jeffery B. Maxson ,  Ann H. McDonald ,  Yun-Yu Wang ,  Keith Kwong Hon Wong ,  Daewon Yang

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L23/53238 ,  H01L21/28556 ,  H01L21/76849 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to a bilayer cap structure for interconnect structures that comprise copper metallization or other conductive metallization. Such bilayer cap structure includes a first cap layer formed by an unbiased high density plasma (HDP) chemical vapor deposition process, and a second cap layer over the first cap layer, where the second cap layer is formed by a biased high density plasma (bHDP) chemical vapor deposition process. During the bHDP chemical vapor deposition process, a low AC bias power is applied to the substrate to increase the ion bombardment on the substrate surface and to induce resputtering of the capping material, thereby forming a seamless second cap layer with excellent reactive ion etching (RIE) selectivity.

摘要翻译： 本发明涉及一种用于互连结构的双层盖结构，其包括铜金属化或其它导电金属化。 这种双层盖结构包括通过无偏高密度等离子体（HDP）化学气相沉积工艺形成的第一盖层和在第一盖层上的第二盖层，其中第二盖层由偏置的高密度等离子体（bHDP ）化学气相沉积工艺。 在bHDP化学气相沉积工艺期间，将低AC偏置功率施加到衬底上以增加衬底表面上的离子轰击并引起封盖材料的再溅射，从而形成具有优异的反应离子蚀刻（RIE）的无缝第二帽层 ）选择性。

公开(公告)号：US06098788A

公开(公告)日：2000-08-08

申请号：US926401

申请日：1997-09-09

申请人： Nancy Anne Greco ,  Ernest Norman Levine ,  Michael F. Lofaro ,  James Gardner Ryan

发明人： Nancy Anne Greco ,  Ernest Norman Levine ,  Michael F. Lofaro ,  James Gardner Ryan

IPC分类号： B29C33/30 ,  B29C33/38 ,  B65G33/00

CPC分类号： B29C33/38 ,  B29C33/302 ,  Y10T428/24322

摘要： A seamless micromechanical object is cast by forming a multilevel mold, filling the mold, and selectively removing the mold with respect to the micromechanical object. The mold can have a first level having a first opening therein, and a second level on the first level, the second level having a second opening therein, the second opening smaller than the first opening. The object may contain a controlled void, for example a micromechanical auger with a void formed therethrough to be used as a capillary to drain off fluids when the auger is in use.

摘要翻译： 通过形成多层模具，填充模具并相对于微机械物体选择性地移除模具来铸造无缝微机械物体。 模具可以具有在其中具有第一开口的第一层和第一层上的第二层，第二层在其中具有第二开口，第二开口小于第一开口。 该物体可以包含受控的空隙，例如具有穿过其形成的空隙的微机械螺旋钻，用作毛细管以在使用螺旋推运器时排出流体。