公开(公告)号：US08455960B2

公开(公告)日：2013-06-04

申请号：US13185112

申请日：2011-07-18

申请人： Frank Jakubowski ,  Peter Baars ,  Till Schloesser

发明人： Frank Jakubowski ,  Peter Baars ,  Till Schloesser

IPC分类号： H01L29/00

CPC分类号： H01L29/517 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/7833

摘要： Semiconductor devices are formed with a silicide interface between the work function layer and polycrystalline silicon. Embodiments include forming a high-k/metal gate stack by: forming a high-k dielectric layer on a substrate, forming a work function metal layer on the high-k dielectric layer, forming a silicide on the work function metal layer, and forming a poly Si layer on the silicide. Embodiments include forming the silicide by: forming a reactive metal layer in situ on the work function layer, forming an a-Si layer in situ on the entire upper surface of the reactive metal layer, and annealing concurrently with forming the poly Si Layer.

摘要翻译： 半导体器件在功函数层与多晶硅之间形成硅化物界面。 实施例包括通过以下方式形成高k /金属栅极堆叠：在衬底上形成高k电介质层，在高k电介质层上形成功函数金属层，在功函数金属层上形成硅化物，以及形成 硅化物上的多晶硅层。 实施例包括：通过在功函数层上原位形成反应性金属层，在反应性金属层的整个上表面上原位形成a-Si层，并与形成多晶硅层同时进行退火来形成硅化物。

公开(公告)号：US08222103B1

公开(公告)日：2012-07-17

申请号：US13027739

申请日：2011-02-15

申请人： Peter Baars ,  Till Schloesser

发明人： Peter Baars ,  Till Schloesser

IPC分类号： H01L21/8242 ,  H01L29/94

CPC分类号： H01L27/10852 ,  H01L23/5223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L27/10817 ,  H01L28/92 ,  H01L2924/0002 ,  H01L2924/00

摘要： Generally, the subject matter disclosed herein relates to a semiconductor device with embedded low-k metallization. A method is disclosed that includes forming a plurality of copper metallization layers that are coupled to a plurality of logic devices in a logic area of a semiconductor device and, after forming the plurality of copper metallization layers, forming a plurality of capacitors in a memory array of the semiconductor device. The capacitors are formed using a non-low-k dielectric material (k value greater than 3), while the copper metallization layers are formed in layers of low-k dielectric material (k value less than 3). A semiconductor device is also disclosed which includes a plurality of logic devices, a memory array comprising a plurality of capacitors, a conductive contact plate coupled to the plurality of capacitors, and a plurality of copper metallization layers coupled to the logic devices, wherein the plurality of copper metallization layers are positioned at a level that is below a level of a bottom surface of the contact plate. A material other than a low-k dielectric material is positioned between the plurality of capacitors in the memory array.

摘要翻译： 通常，这里公开的主题涉及具有嵌入式低k金属化的半导体器件。 公开了一种方法，其包括形成耦合到半导体器件的逻辑区域中的多个逻辑器件的多个铜金属化层，并且在形成多个铜金属化层之后，在存储器阵列中形成多个电容器 的半导体器件。 使用非低k电介质材料（k值大于3）形成电容器，而铜金属化层以低k电介质材料（k值小于3）形成。 还公开了一种半导体器件，其包括多个逻辑器件，包括多个电容器的存储器阵列，耦合到多个电容器的导电接触板以及耦合到逻辑器件的多个铜金属化层，其中多个 的铜金属化层被定位在低于接触板的底表面的水平的水平。 除了低k电介质材料之外的材料位于存储器阵列中的多个电容器之间。

公开(公告)号：US20130049089A1

公开(公告)日：2013-02-28

申请号：US13218262

申请日：2011-08-25

申请人： Peter Baars ,  Till Schloesser

发明人： Peter Baars ,  Till Schloesser

IPC分类号： H01L21/8242 ,  H01L27/06

CPC分类号： H01L21/84 ,  H01L27/0207 ,  H01L27/1087 ,  H01L27/1203 ,  H01L28/91

摘要： Methods are provided for fabricating an integrated circuit that includes a deep trench capacitor. One method includes fabricating a plurality of transistors on a semiconductor substrate, the plurality of transistors each including gate structures, source and drain regions, and silicide contacts to the source and drain regions. A trench is then etched into the semiconductor substrate in proximity to the drain region of a selected transistor. The trench is filled with a layer of metal in contact with the semiconductor substrate, a layer of dielectric material overlying the layer of metal, and a second metal overlying the layer of dielectric material. A metal contact is then formed coupling the second metal to the silicide contact on the drain region of the selected transistor. A bit line is formed contacting the source region of the selected transistor and a word line is formed contacting the gate structure of the transistor.

摘要翻译： 提供了用于制造包括深沟槽电容器的集成电路的方法。 一种方法包括在半导体衬底上制造多个晶体管，所述多个晶体管各自包括栅极结构，源极和漏极区以及到源极和漏极区的硅化物接触。 然后在所选择的晶体管的漏极区域附近将沟槽蚀刻到半导体衬底中。 沟槽填充有与半导体衬底接触的金属层，覆盖金属层的电介质材料层和覆盖在介电材料层上的第二金属。 然后形成金属接触，将第二金属耦合到所选晶体管的漏极区上的硅化物接触。 与所选择的晶体管的源极区域接触的位线形成为与晶体管的栅极结构接触的字线。

公开(公告)号：US20130020656A1

公开(公告)日：2013-01-24

申请号：US13185112

申请日：2011-07-18

申请人： Frank Jakubowski ,  Peter Baars ,  Till Schloesser

发明人： Frank Jakubowski ,  Peter Baars ,  Till Schloesser

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/517 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/7833

摘要： Semiconductor devices are formed with a silicide interface between the work function layer and polycrystalline silicon. Embodiments include forming a high-k/metal gate stack by: forming a high-k dielectric layer on a substrate, forming a work function metal layer on the high-k dielectric layer, forming a silicide on the work function metal layer, and forming a poly Si layer on the silicide. Embodiments include forming the silicide by: forming a reactive metal layer in situ on the work function layer, forming an a-Si layer in situ on the entire upper surface of the reactive metal layer, and annealing concurrently with forming the poly Si Layer.

摘要翻译： 半导体器件在功函数层与多晶硅之间形成硅化物界面。 实施例包括通过以下方式形成高k /金属栅极堆叠：在衬底上形成高k电介质层，在高k电介质层上形成功函数金属层，在功函数金属层上形成硅化物，以及形成 硅化物上的多晶硅层。 实施例包括：通过在功函数层上原位形成反应性金属层，在反应性金属层的整个上表面上原位形成a-Si层，并与形成多晶硅层同时进行退火来形成硅化物。

公开(公告)号：US20120322225A1

公开(公告)日：2012-12-20

申请号：US13164272

申请日：2011-06-20

申请人： Till Schloesser ,  Peter Baars

发明人： Till Schloesser ,  Peter Baars

IPC分类号： H01L21/02

CPC分类号： H01L27/10894 ,  H01L21/76816 ,  H01L21/76895 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10888

摘要： A method is disclosed that includes forming a conductive logic contact in a logic area of a semiconductor device, forming a bit line contact and a capacitor contact in a memory array of the semiconductor device, and performing at least one first common process to form a first metallization layer comprising a first conductive line in the logic area that is conductively coupled to the conductive logic contact and a bit line in the memory array that is conductively coupled to the bit line contact. The method further includes performing at least one second common process to form a second metallization layer comprising a first conductive structure conductively coupled to the first conductive line in the logic area and a second conductive structure in the memory array that that is conductively coupled to the capacitor contact.

摘要翻译： 公开了一种方法，其包括在半导体器件的逻辑区域中形成导电逻辑触点，在半导体器件的存储器阵列中形成位线接触和电容器触点，以及执行至少一个第一公共工艺以形成第一 金属化层包括在逻辑区域中的导电耦合到导电逻辑触点的第一导线和存储器阵列中与导线耦合到位线触点的位线。 所述方法还包括执行至少一个第二公共处理以形成第二金属化层，所述第二金属化层包括导电耦合到所述逻辑区域中的所述第一导电线的第一导电结构和所述存储器阵列中的导电耦合到所述电容器的第二导电结构 联系。

公开(公告)号：US07687343B2

公开(公告)日：2010-03-30

申请号：US11633090

申请日：2006-12-04

申请人： Peter Moll ,  Peter Baars ,  Till Schloesser ,  Rolf Weis ,  Klaus Muemmler

发明人： Peter Moll ,  Peter Baars ,  Till Schloesser ,  Rolf Weis ,  Klaus Muemmler

IPC分类号： H01L21/8242

CPC分类号： H01L28/90 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10894 ,  H01L27/10897

摘要： A storage capacitor includes a first capacitor portion and a second capacitor portion, the second capacitor portion being disposed above the first capacitor portion, thereby defining a first direction. The first and the second portions each include a hollow body made of a conductive material, respectively, thereby forming a first capacitor electrode. An upper diameter of each of the hollow bodies is larger than a lower diameter of the hollow body, the diameter being measured perpendicularly with respect to the first direction. The storage capacitor also includes a second capacitor electrode and a dielectric material disposed between the first and the second capacitor electrodes. The storage capacitor also includes an insulating material disposed outside the hollow bodies, and a layer of an insulating material. A lower side of the insulating layer is disposed at a height of an upper side of the first capacitor portion.

摘要翻译： 存储电容器包括第一电容器部分和第二电容器部分，第二电容器部分设置在第一电容器部分上方，从而限定第一方向。 第一和第二部分分别包括由导电材料制成的中空体，从而形成第一电容器电极。 每个中空体的上直径大于中空体的下直径，其直径相对于第一方向垂直地被测量。 存储电容器还包括设置在第一和第二电容器电极之间的第二电容器电极和介电材料。 存储电容器还包括设置在中空体外部的绝缘材料和绝缘材料层。 绝缘层的下侧设置在第一电容器部分的上侧的高度处。

公开(公告)号：US20080128773A1

公开(公告)日：2008-06-05

申请号：US11633090

申请日：2006-12-04

申请人： Peter Moll ,  Peter Baars ,  Till Schloesser ,  Rolf Weis ,  Klaus Muemmler

发明人： Peter Moll ,  Peter Baars ,  Till Schloesser ,  Rolf Weis ,  Klaus Muemmler

IPC分类号： H01L27/108

CPC分类号： H01L28/90 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10894 ,  H01L27/10897

摘要： A storage capacitor includes a first capacitor portion and a second capacitor portion, the second capacitor portion being disposed above the first capacitor portion, thereby defining a first direction. The first and the second portions each include a hollow body made of a conductive material, respectively, thereby forming a first capacitor electrode. An upper diameter of each of the hollow bodies is larger than a lower diameter of the hollow body, the diameter being measured perpendicularly with respect to the first direction. The storage capacitor also includes a second capacitor electrode and a dielectric material disposed between the first and the second capacitor electrodes. The storage capacitor also includes an insulating material disposed outside the hollow bodies, and a layer of an insulating material. A lower side of the insulating layer is disposed at a height of an upper side of the first capacitor portion.

摘要翻译： 存储电容器包括第一电容器部分和第二电容器部分，第二电容器部分设置在第一电容器部分上方，从而限定第一方向。 第一和第二部分分别包括由导电材料制成的中空体，从而形成第一电容器电极。 每个中空体的上直径大于中空体的下直径，其直径相对于第一方向垂直地被测量。 存储电容器还包括设置在第一和第二电容器电极之间的第二电容器电极和介电材料。 存储电容器还包括设置在中空体外部的绝缘材料和绝缘材料层。 绝缘层的下侧设置在第一电容器部分的上侧的高度处。

公开(公告)号：US08853810B2

公开(公告)日：2014-10-07

申请号：US13218262

申请日：2011-08-25

申请人： Peter Baars ,  Till Schloesser

发明人： Peter Baars ,  Till Schloesser

IPC分类号： H01L27/108 ,  H01L21/8242 ,  H01L27/12 ,  H01L21/84 ,  H01L27/02 ,  H01L49/02

CPC分类号： H01L21/84 ,  H01L27/0207 ,  H01L27/1087 ,  H01L27/1203 ,  H01L28/91

摘要： Methods are provided for fabricating an integrated circuit that includes a deep trench capacitor. One method includes fabricating a plurality of transistors on a semiconductor substrate, the plurality of transistors each including gate structures, source and drain regions, and silicide contacts to the source and drain regions. A trench is then etched into the semiconductor substrate in proximity to the drain region of a selected transistor. The trench is filled with a layer of metal in contact with the semiconductor substrate, a layer of dielectric material overlying the layer of metal, and a second metal overlying the layer of dielectric material. A metal contact is then formed coupling the second metal to the silicide contact on the drain region of the selected transistor. A bit line is formed contacting the source region of the selected transistor and a word line is formed contacting the gate structure of the transistor.

摘要翻译： 提供了用于制造包括深沟槽电容器的集成电路的方法。 一种方法包括在半导体衬底上制造多个晶体管，所述多个晶体管各自包括栅极结构，源极和漏极区以及到源极和漏极区的硅化物接触。 然后在所选择的晶体管的漏极区域附近将沟槽蚀刻到半导体衬底中。 沟槽填充有与半导体衬底接触的金属层，覆盖金属层的电介质材料层和覆盖在介电材料层上的第二金属。 然后形成金属接触，将第二金属耦合到所选晶体管的漏极区上的硅化物接触。 与所选择的晶体管的源极区域接触的位线形成为与晶体管的栅极结构接触的字线。

公开(公告)号：US08835245B2

公开(公告)日：2014-09-16

申请号：US13372604

申请日：2012-02-14

申请人： Peter Baars ,  Till Schloesser ,  Frank Jakubowski ,  Andy Wei ,  Richard Carter ,  Matthias Schaller

发明人： Peter Baars ,  Till Schloesser ,  Frank Jakubowski ,  Andy Wei ,  Richard Carter ,  Matthias Schaller

IPC分类号： H01L21/8234 ,  H01L21/768 ,  H01L21/285 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823475 ,  H01L21/28518 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823437 ,  H01L29/66636 ,  H01L29/7848

摘要： When forming sophisticated semiconductor devices, a replacement gate approach may be applied in combination with a self-aligned contact regime by forming the self-aligned contacts prior to replacing the placeholder material of the gate electrode structures.

摘要翻译： 当形成复杂的半导体器件时，可以在替换栅电极结构的占位符材料之前形成自对准触点，将替代栅极方法与自对准的接触方式结合使用。

公开(公告)号：US08790975B2

公开(公告)日：2014-07-29

申请号：US13040975

申请日：2011-03-04

申请人： Peter Baars ,  Till Schloesser ,  Vivien Schroeder

发明人： Peter Baars ,  Till Schloesser ,  Vivien Schroeder

IPC分类号： H01L21/8242 ,  H01L21/20 ,  H01L21/28 ,  H01L21/768 ,  H01L21/02 ,  H01L27/108

CPC分类号： H01L21/76877 ,  H01L21/02697 ,  H01L21/28 ,  H01L23/5223 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/87 ,  H01L28/91 ,  H01L29/665 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： When forming capacitive structures in a metallization system, such as in a dynamic RAM area, placeholder metal regions may be formed together with “regular” metal features, thereby achieving a very efficient overall process flow. At a certain manufacturing stage, the metal of the placeholder metal region may be removed on the basis of a wet chemical etch recipe followed by the deposition of the electrode materials and the dielectric materials for the capacitive structure without unduly affecting other portions of the metallization system. In this manner, very high capacitance values may be realized on the basis of a very efficient overall manufacturing flow.

摘要翻译： 当在诸如动态RAM区域的金属化系统中形成电容结构时，可以与“规则”金属特征一起形成占位符金属区域，从而实现非常有效的整体工艺流程。 在某个制造阶段，可以基于湿式化学蚀刻配方去除占位金属区域的金属，随后沉积用于电容结构的电极材料和电介质材料，而不会过度影响金属化系统的其它部分 。 以这种方式，可以在非常有效的总体制造流程的基础上实现非常高的电容值。