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公开(公告)号：US06205571B1
公开(公告)日：2001-03-20
申请号：US09222143
申请日：1998-12-29
申请人： Peter J. Camporese , Alina Deutsch , Timothy Gerard McNamara , Phillip John Restle , David Allan Webber
发明人： Peter J. Camporese , Alina Deutsch , Timothy Gerard McNamara , Phillip John Restle , David Allan Webber
IPC分类号： G06F1750
CPC分类号： G06F1/10 , G06F17/5077
摘要： An X-Y grid tree clock distribution network for distributing a clock signal across a VLSI chip. Tunable wiring tree networks are combined with an X-Y grid vertically and horizontally connecting all the tree end points. No drivers are necessary at connection points of the tree end points to the X-Y grid. The final X-Y grid distributes the clock signal close to every place it is needed, and reduces skew across local regions. A tuning method allows buffering of the clock signal, while minimizing both nominal clock skew and clock uncertainty. The tuned tree networks provide low skew even with variations in clock load density and non-ideal buffer placement, while minimizing the number of buffers needed. The tuning method first represents a total capacitance of one or more of clock pin loads and twig wiring as a clustered grid load. Next, a smoothing of the clustered grid loads approximates the effect of the X-Y grid. Electrical simulation models are created for network components and clustered grid loads are substituted with smoothed clustered grid loads. A set of NSECTOR electrical net lists are next created by extracting a net list with associated X-Y grid wires cut to isolate each sector net list from its neighboring sectors. Each NSECTOR electrical net list is then tuned, wherein the smoothed clustered grid loads represent an approximation of the effects of the neighboring sectors of each NSECTOR electrical net list.
摘要翻译： 一个用于在VLSI芯片上分配时钟信号的X-Y网格树时钟分配网络。 可调式接线树网络与X-Y网格结合，垂直和水平连接所有树端点。 在X-Y网格的树端点的连接点不需要驱动程序。 最后的X-Y网格将时钟信号分配到每个需要的地方，并减少局部区域的偏差。 调谐方法允许缓冲时钟信号，同时最小化标称时钟偏移和时钟不确定度。 调谐树网络即使在时钟负载密度和非理想缓冲器放置的变化下也提供低偏移，同时最小化所需的缓冲器数量。 调谐方法首先表示作为集群电网负载的一个或多个时钟引脚负载和布线布线的总电容。 接下来，聚类网格负载的平滑近似于X-Y网格的效果。 为网络组件创建电气仿真模型，并且使用平滑的集群网格负载代替集群网格负载。 接下来通过提取具有相关联的X-Y网格线的网络列表来创建一组NSECTOR电网列表，以将每个扇区网络列表与其相邻扇区隔离。 然后调整每个NSECTOR电网列表，其中平滑的集群网格负载表示每个NSECTOR电网列表的相邻扇区的影响的近似值。
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2.发明授权X-Y grid tree clock distribution network with tunable tree and grid networks 失效具有可调树和网格网络的X-Y网格树时钟分配网络公开(公告)号：US06311313B1
公开(公告)日：2001-10-30
申请号：US09222141
申请日：1998-12-29
申请人： Peter J. Camporese , Alina Deutsch , Timothy Gerard McNamara , Phillip John Restle , David Allan Webber
发明人： Peter J. Camporese , Alina Deutsch , Timothy Gerard McNamara , Phillip John Restle , David Allan Webber
IPC分类号： G06F945
CPC分类号： G06F1/10
摘要： An X-Y grid tree clock distribution network for distributing a clock signal across a VLSI chip. Tunable wiring tree networks are combined with an X-Y grid vertically and horizontally connecting all the tree end points. No drivers are necessary at connection points of the tree end points to the X-Y grid. The final X-Y grid distributes the clock signal close to every place it is needed, and reduces skew across local regions. A tuning method allows buffering of the clock signal, while minimizing both nominal clock skew and clock uncertainty. The tuned tree networks provide low skew even with variations in clock load density and non-ideal buffer placement, while minimizing the number of buffers needed. The tuning method first represents a total capacitance of one or more of clock pin loads and twig wiring as a clustered grid load. Next, a smoothing of the clustered grid loads approximates the effect of the X-Y grid. Electrical simulation models are created for network components and clustered grid loads are substituted with smoothed clustered grid loads. A set of NSECTOR electrical net lists are next created by extracting a net list with associated X-Y grid wires cut to isolate each sector net list from its neighboring sectors. Each NSECTOR electrical net list is then tuned, wherein the smoothed clustered grid loads represent an approximation of the effects of the neighboring sectors of each NSECTOR electrical net list.
摘要翻译： 一个用于在VLSI芯片上分配时钟信号的X-Y网格树时钟分配网络。 可调式接线树网络与X-Y网格结合，垂直和水平连接所有树端点。 在X-Y网格的树端点的连接点不需要驱动程序。 最后的X-Y网格将时钟信号分配到每个需要的地方，并减少局部区域的偏差。 调谐方法允许缓冲时钟信号，同时最小化标称时钟偏移和时钟不确定度。 调谐树网络即使在时钟负载密度和非理想缓冲器放置的变化下也提供低偏移，同时最小化所需的缓冲器数量。 调谐方法首先表示作为集群电网负载的一个或多个时钟引脚负载和布线布线的总电容。 接下来，聚类网格负载的平滑近似于X-Y网格的效果。 为网络组件创建电气仿真模型，并且使用平滑的集群网格负载代替集群网格负载。 接下来通过提取具有相关联的X-Y网格线的网络列表来创建一组NSECTOR电网列表，以将每个扇区网络列表与其相邻扇区隔离。 然后调整每个NSECTOR电网列表，其中平滑的集群网格负载表示每个NSECTOR电网列表的相邻扇区的影响的近似值。
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3.发明授权System and method for reducing calculation complexity of lossy, frequency-dependent transmission-line computation 失效用于降低有损耗，频率依赖传输线计算的计算复杂度的系统和方法公开(公告)号：US06342823B1
公开(公告)日：2002-01-29
申请号：US09140643
申请日：1998-08-26
申请人： Allan Harvey Dansky , Alina Deutsch , Gerard Vincent Kopcsay , Phillip John Restle , Howard Harold Smith
发明人： Allan Harvey Dansky , Alina Deutsch , Gerard Vincent Kopcsay , Phillip John Restle , Howard Harold Smith
IPC分类号： H01P500
CPC分类号： G06F17/5036
摘要： A method and system for reducing the computation complexity and improving accuracy of delay and crosstalk calculation in transmission-lines with frequency-dependent losses. An analysis tool based on restricted coupled-line topologies, simple two-dimensional to three-dimensional RLC matrix conversion, and use of prestored synthesized circuits that accurately capture frequency-dependent loss effects. The CAD tool can handle frequency-dependent resistive and inductive effects for coupled-interconnections on large microprocessor chips with >10K of critical nets. This is done in an interactive manner during the design cycle and allows first path fast product design.
摘要翻译： 一种降低计算复杂度，提高频率依赖损耗的传输线延迟和串扰计算精度的方法和系统。 基于限制耦合线拓扑的分析工具，简单的二维至三维RLC矩阵转换，以及使用准备捕获频率相关损耗效应的预存储合成电路。 CAD工具可以处理具有> 10K关键网络的大型微处理器芯片上的耦合互连的频率相关电阻和电感效应。 这在设计周期中以交互的方式完成，并允许第一路径快速产品设计。
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公开(公告)号：US20130229189A1
公开(公告)日：2013-09-05
申请号：US13411068
申请日：2012-03-02
IPC分类号： G01R31/14
CPC分类号： G01R31/3008
摘要： A test circuit for detecting a leakage defect in a circuit under test includes a test stimulus circuit operative to drive an otherwise defect-free, characteristically capacitive node in the circuit under test to a prescribed voltage level, and an observation circuit having at least one threshold and adapted for connection with at least one node in the circuit under test. The observation circuit is operative to detect a voltage level of the node in the circuit under test and to generate an output signal indicative of whether the voltage level of the node is less than the threshold. The voltage level of the node being less than the threshold is indicative of a first type of leakage defect, and the voltage level of the node being greater than the threshold is indicative of a second type of leakage defect.
摘要翻译： 一种用于检测被测电路中的泄漏缺陷的测试电路包括一个测试激励电路，用于将被测电路中的其它无缺陷特征电容性节点驱动到规定的电压电平，以及具有至少一个阈值的观测电路 并且适于与被测电路中的至少一个节点连接。 观察电路可操作以检测被测电路中的节点的电压电平并产生指示节点的电压电平是否小于阈值的输出信号。 节点小于阈值的电压电平表示第一类型的漏电缺陷，并且节点大于阈值的电压电平表示第二类泄漏缺陷。
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5.发明申请Self-Learning of the Optimal Power or Performance Operating Point of a Computer Chip Based on Instantaneous Feedback of Present Operating Environment 有权基于当前操作环境的瞬时反馈的计算机芯片的最佳功率或性能工作点的自学习公开(公告)号：US20090312848A1
公开(公告)日：2009-12-17
申请号：US12139928
申请日：2008-06-16
IPC分类号： G05B13/02
CPC分类号： G05B19/0428 , G05B2219/23399 , G05B2219/25064
摘要： Sensors on the integrated circuit are used to detect the current operating state of the chip, such as frequency, voltage, temperature characteristics, or variation in the integrated circuit manufacturing process. In response, the integrated circuit may choose to modify operational parameters (such as frequency, voltage, or power-down states) in order to dynamically and autonomously maintain an optimal performance and/or power-efficiency operational point.
摘要翻译： 集成电路中的传感器用于检测芯片的当前工作状态，例如频率，电压，温度特性或集成电路制造过程中的变化。 作为响应，集成电路可以选择修改操作参数（例如频率，电压或掉电状态），以便动态地和自主地维持最佳性能和/或功率效率操作点。
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公开(公告)号：US6006025A
公开(公告)日：1999-12-21
申请号：US934995
申请日：1997-09-22
CPC分类号： G06F17/5077 , G06F1/10 , G06F2217/62
摘要： A method of wire routing includes the steps of providing an array of cells on a semiconductor chip, determining a minimum distance location between a first clock point, an second clock point and a drive point for connecting to a connection point in the array of cells, and defining a wire path through an array of blockages disposed in the array of cells from the minimum distance location to the first clock point and from the minimum distance location to the second clock point to create a path for a wire for connecting the first clock point and the second clock point to a connection point such that skew is minimized between the starting clock point and the second clock point from the connection point when a clock signal is provided to the connection point from the drive point.
摘要翻译： 线路布线方法包括以下步骤：在半导体芯片上提供单元阵列，确定第一时钟点，第二时钟点和连接到单元阵列中的连接点的驱动点之间的最小距离位置， 以及通过设置在所述小区阵列中的阻塞阵列从所述最小距离位置到所述第一时钟点以及从所述最小距离位置到所述第二时钟点来定义有线路径，以创建用于连接所述第一时钟点的线路的路径 并且第二时钟点指向连接点，使得当从驱动点向连接点提供时钟信号时，从连接点开始时钟点和第二时钟点之间的偏移最小化。
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公开(公告)号：US08860425B2
公开(公告)日：2014-10-14
申请号：US13411068
申请日：2012-03-02
IPC分类号： G01R31/14
CPC分类号： G01R31/3008
摘要： A test circuit for detecting a leakage defect in a circuit under test includes a test stimulus circuit operative to drive an otherwise defect-free, characteristically capacitive node in the circuit under test to a prescribed voltage level, and an observation circuit having at least one threshold and adapted for connection with at least one node in the circuit under test. The observation circuit is operative to detect a voltage level of the node in the circuit under test and to generate an output signal indicative of whether the voltage level of the node is less than the threshold. The voltage level of the node being less than the threshold is indicative of a first type of leakage defect, and the voltage level of the node being greater than the threshold is indicative of a second type of leakage defect.
摘要翻译： 一种用于检测被测电路中的泄漏缺陷的测试电路包括一个测试激励电路，用于将被测电路中的其它无缺陷特征电容性节点驱动到规定的电压电平，以及具有至少一个阈值的观测电路 并且适于与被测电路中的至少一个节点连接。 观察电路可操作以检测被测电路中的节点的电压电平并产生指示节点的电压电平是否小于阈值的输出信号。 节点小于阈值的电压电平表示第一类型的漏电缺陷，并且节点大于阈值的电压电平表示第二类泄漏缺陷。
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公开(公告)号：US20120313647A1
公开(公告)日：2012-12-13
申请号：US13156836
申请日：2011-06-09
IPC分类号： G01R27/28
CPC分类号： G11C29/025 , G01R31/2882 , G11C7/10 , G11C29/50012 , H01L25/0657 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A method and system for an infrastructure for performance-based chip-to-chip stacking are provided in the illustrative embodiments. A critical path monitor circuit (infrastructure) is configured to launch a signal from a launch point in a first layer, the first layer being a first circuit. The infrastructure is further configured to create an electrical path to a capture point. The signal is launched from the launch point in the first layer. A performance characteristic of the electrical path is measured, resulting in a measurement, wherein the measurement is indicative of a performance of the first layer when stacked with a second layer in a 3D stack without actually stacking the first and the second layers in the 3D stack, the second layer being a second circuit.
摘要翻译： 在说明性实施例中提供了用于基于性能的芯片到芯片堆叠的基础设施的方法和系统。 关键路径监控电路（基础设施）被配置为从第一层中的发射点发射信号，第一层是第一电路。 基础设施还被配置为创建到捕获点的电路径。 信号从第一层的发射点发射。 测量电路径的性能特征，从而进行测量，其中测量表示当与3D堆叠中的第二层堆叠时的第一层的性能，而不会在3D堆叠中实际堆叠第一层和第二层 ，第二层是第二电路。
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9.发明授权Minimizing clock uncertainty on clock distribution networks using a multi-level de-skewing technique 失效使用多级去偏移技术最小化时钟分配网络上的时钟不确定性公开(公告)号：US07941689B2
公开(公告)日：2011-05-10
申请号：US12051834
申请日：2008-03-19
IPC分类号： G06F1/04 , H03K19/173 , H01L25/00
CPC分类号： G06F1/10
摘要： Disclosed is a method of minimizing clock uncertainty using a multi-level de-skewing technique. The method includes the steps of obtaining a chip wherein at least a portion of the chip has a regular array of buffers on multiple levels, the buffers being driven by first drivers and the first drivers being driven by second drivers; grouping the buffers in a first direction to create clusters with the same number of buffer inputs, wherein if there are not the same number of buffer inputs in each cluster, then adding dummy buffers to the cluster with a deficient number of buffer inputs; wiring outputs of the first drivers together in a second direction, wherein the first and second directions are orthogonal; and wiring outputs of the second together in the second direction.
摘要翻译： 公开了使用多级去偏移技术来最小化时钟不确定性的方法。 该方法包括以下步骤：获得芯片，其中芯片的至少一部分在多个级别上具有规则的缓冲器阵列，缓冲器由第一驱动器驱动，第一驱动器由第二驱动器驱动; 在第一方向上对缓冲器进行分组以产生具有相同数量的缓冲器输入的簇，其中如果每个簇中没有相同数量的缓冲器输入，则向具有缺少数量的缓冲器输入的簇添加虚拟缓冲器; 所述第一驱动器的接线输出沿第二方向一起，其中所述第一和第二方向是正交的; 并且在第二方向上将第二组件的输出连接在一起。
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10.发明申请MINIMIZING CLOCK UNCERTAINTY ON CLOCK DISTRIBUTION NETWORKS USING A MULTI-LEVEL DE-SKEWING TECHNIQUE 失效使用多级删除技术在时钟分配网络上最小化时钟不确定度公开(公告)号：US20090237134A1
公开(公告)日：2009-09-24
申请号：US12051834
申请日：2008-03-19
IPC分类号： H03K5/01
CPC分类号： G06F1/10
摘要： Disclosed is a method of minimizing clock uncertainty using a multi-level de-skewing technique. The method includes the steps of obtaining a chip wherein at least a portion of the chip has a regular array of buffers on multiple levels, the buffers being driven by first drivers and the first drivers being driven by second drivers; grouping the buffers in a first direction to create clusters with the same number of buffer inputs, wherein if there are not the same number of buffer inputs in each cluster, then adding dummy buffers to the cluster with a deficient number of buffer inputs; wiring outputs of the first drivers together in a second direction, wherein the first and second directions are orthogonal; and wiring outputs of the second together in the second direction.
摘要翻译： 公开了使用多级去偏移技术来最小化时钟不确定性的方法。 该方法包括以下步骤：获得芯片，其中芯片的至少一部分在多个级别上具有规则的缓冲器阵列，缓冲器由第一驱动器驱动，第一驱动器由第二驱动器驱动; 在第一方向上对缓冲器进行分组以产生具有相同数量的缓冲器输入的簇，其中如果每个簇中没有相同数量的缓冲器输入，则向具有缺少数量的缓冲器输入的簇添加虚拟缓冲器; 所述第一驱动器的接线输出沿第二方向一起，其中所述第一和第二方向是正交的; 并且在第二方向上将第二组件的输出连接在一起。
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