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21 条记录 (耗时 0.03 秒)

    TWO PFET SOI MEMORY CELLS
    5.
    发明申请
    TWO PFET SOI MEMORY CELLS 审中-公开
    两个PFET SOI存储器单元

    公开(公告)号：US20110101440A1

    公开(公告)日：2011-05-05

    申请号：US12612710

    申请日：2009-11-05

    申请人： Jin Cai ,  Brian L. Ji ,  Tak Hung Ning

    发明人： Jin Cai ,  Brian L. Ji ,  Tak Hung Ning

    IPC分类号： H01L27/092 ,  H01L21/8238

    CPC分类号： H01L27/1203 ,  H01L21/823425 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/792

    摘要： A CMOS device includes a silicon substrate and an electrical insulator formed over the silicon substrate. The device also includes an access pFET formed over the electrical insulator and a first gate stack and a storage pFET formed over the electrical insulator, the storage pFET including a second source region that is co-formed with the first drain region, a second channel region, and a second drain region. The device also includes a second gate stack including a second dielectric layer formed above the second channel region and a floating gate electrode formed above the second gate dielectric layer.

    摘要翻译： CMOS器件包括硅衬底和形成在硅衬底上的电绝缘体。 器件还包括形成在电绝缘体上的访问pFET和形成在电绝缘体上的第一栅极堆叠和存储pFET，存储pFET包括与第一漏极区域共同形成的第二源极区域，第二沟道区域 ，和第二漏区。 该器件还包括第二栅极堆叠，其包括形成在第二沟道区上方的第二介电层和形成在第二栅极介电层上方的浮置栅电极。

    SOI FET with source-side body doping
    6.
    发明授权
    SOI FET with source-side body doping 有权
    具有源极体掺杂的SOI FET

    公开(公告)号：US07867866B2

    公开(公告)日：2011-01-11

    申请号：US12651499

    申请日：2010-01-04

    申请人： Jin Cai ,  Tak Hung Ning

    发明人： Jin Cai ,  Tak Hung Ning

    IPC分类号： H01L21/336 ,  H01L31/119

    CPC分类号： H01L29/78612 ,  H01L29/66772

    摘要： An SOI FET device with improved floating body is proposed. Control of the body potential is accomplished by having a body doping concentration next to the source electrode higher than the body doping concentration next to the drain electrode. The high source-side dopant concentration leads to elevated forward leakage current between the source electrode and the body, which leakage current effectively locks the body potential to the source electrode potential. Furthermore, having the source-to-body junction capacitance larger than the drain-to-body junction capacitance has additional advantages in device operation. The device has no structure fabricated for the purpose of electrically connecting the body potential to other elements of the device.

    摘要翻译： 提出了一种具有改进的浮体的SOI FET器件。 体电位的控制是通过使源电极旁边的体掺杂浓度高于漏电极旁边的体掺杂浓度来实现的。 高源侧掺杂剂浓度导致源电极和体之间的向前泄漏电流升高，这种泄漏电流有效地将体电位锁定到源极电位。 此外，具有大于漏极 - 体结结电容的源极 - 体结结电容在器件操作中具有额外的优点。 该装置没有制造用于将身体电势电连接到装置的其它元件的结构。

    Contact resistivity reduction in transistor devices by deep level impurity formation
    7.
    发明授权
    Contact resistivity reduction in transistor devices by deep level impurity formation 有权
    深层杂质形成对晶体管器件的接触电阻率降低

    公开(公告)号：US08557693B2

    公开(公告)日：2013-10-15

    申请号：US12793046

    申请日：2010-06-03

    申请人： Tak Hung Ning ,  Zhen Zhang

    发明人： Tak Hung Ning ,  Zhen Zhang

    IPC分类号： H01L21/22

    CPC分类号： H01L29/0847 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/456 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming a low resistance contact structure in a semiconductor device includes forming a doped semiconductor region in a semiconductor substrate; forming a deep level impurity region at an upper portion of the doped semiconductor region; activating dopants in both the doped semiconductor region and the deep level impurity region by annealing; and forming a metal contact over the deep level impurity region so as to create a metal-semiconductor interface therebetween.

    摘要翻译： 在半导体器件中形成低电阻接触结构的方法包括在半导体衬底中形成掺杂半导体区域; 在所述掺杂半导体区域的上部形成深层杂质区域; 通过退火激活掺杂半导体区域和深层杂质区域中的掺杂剂; 以及在深层杂质区上形成金属接触，从而在它们之间产生金属 - 半导体界面。

    Graded-base-bandgap bipolar transistor having a constant—bandgap in the base
    8.
    发明授权
    Graded-base-bandgap bipolar transistor having a constant—bandgap in the base 失效
    在基极中具有恒定带隙的梯度基带隙双极晶体管

    公开(公告)号：US07170112B2

    公开(公告)日：2007-01-30

    申请号：US10283705

    申请日：2002-10-30

    申请人： Tak Hung Ning

    发明人： Tak Hung Ning

    IPC分类号： H01L29/739 ,  H01L31/0328 ,  H01L31/0336

    CPC分类号： H01L29/66242 ,  H01L29/1004 ,  H01L29/66318 ,  H01L29/7371 ,  H01L29/7378

    摘要： A bipolar transistor structure and process technology is described incorporating a emitter, a base, and a collector, with most of the intrinsic base adjacent the collector having a graded energy bandgap and a layer of the intrinsic base adjacent the emitter having a substantially constant energy bandgap. The invention has a smaller base transit time than a conventional graded-base-bandgap bipolar transistor.

    摘要翻译： 描述了双极晶体管结构和工艺技术，其结合了发射极，基极和集电极，其中与集电极相邻的大部分本征基极具有梯度能带隙和邻近发射极的本征基极层具有基本恒定的能带隙 。 本发明具有比传统的梯度基带隙双极晶体管更小的基极传输时间。

    Method of making EEPROM having coplanar on-insulator FET and control gate
    9.
    发明授权
    Method of making EEPROM having coplanar on-insulator FET and control gate 失效
    制造具有共面绝缘体FET和控制栅极的EEPROM的方法

    公开(公告)号：US5960265A

    公开(公告)日：1999-09-28

    申请号：US881628

    申请日：1997-06-24

    申请人： Alexandre Acovic ,  Tak Hung Ning ,  Paul Michael Solomon

    发明人： Alexandre Acovic ,  Tak Hung Ning ,  Paul Michael Solomon

    IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L27/12 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/115 ,  H01L27/1203 ,  H01L29/42324 ,  H01L29/7881

    摘要： An EEPROM device is described incorporating a field effect transistor and a control gate spaced apart on a first insulating layer, a second insulating layer formed over the field effect transistor and the control gate and a common floating gate on the second insulating layer over the channel of the field effect transistor and the control gate, the floating gate thus also forms the gate electrode of the field-effect transistor. The EEPROM devices may be interconnected in a memory array and a plurality of memory arrays may be stacked on upon another. The invention overcomes the problem of using a non-standard silicon-on-insulator (SOI) CMOS process to make EEPROM arrays with high areal density.

    摘要翻译： 描述了一种EEPROM器件，其结合了场效应晶体管和在第一绝缘层上间隔开的控制栅极，在场效应晶体管上形成的第二绝缘层和控制栅极以及在第二绝缘层上的公共浮置栅极 场效应晶体管和控制栅极，因此浮置栅极也形成场效应晶体管的栅电极。 EEPROM器件可以互连在存储器阵列中，并且多个存储器阵列可以堆叠在另一个上。 本发明克服了使用非标准绝缘体上硅（SOI）CMOS工艺来制造具有高面密度的EEPROM阵列的问题。

    FET and/or bipolar devices formed in thin vertical silicon on insulator (SOI) structures
    10.
    发明授权
    FET and/or bipolar devices formed in thin vertical silicon on insulator (SOI) structures 失效

    公开(公告)号：US5723370A

    公开(公告)日：1998-03-03

    申请号：US713061

    申请日：1996-09-12

    申请人： Tak Hung Ning ,  Ben Song Wu

    发明人： Tak Hung Ning ,  Ben Song Wu

    IPC分类号： H01L21/331 ,  H01L21/336 ,  H01L27/12 ,  H01L29/786 ,  H01L21/84

    CPC分类号： H01L29/66265 ,  H01L27/1203 ,  H01L29/66666 ,  H01L29/78642

    摘要： A process for fabricating Ultra Large Scale Integrated (ULSI) circuits in Silicon On Insulator (SOI) technology in which the device structures, which can be bipolar, FET, or a combination, are formed in vertical silicon sidewalls having insulation under and in back thereof so as to create SKI device structures. The silicon sidewall device SOI structures, when fabricated, take the form of cells with each cell having a plurality of either bipolar devices, FET devices, or a combination of these devices, such as collectors, emitters, bases, sources, drains, and gates interconnected within the planes of the regions of the devices in the cells and can be interconnected within the planes of the regions of devices in adjacent cells. Further, the interconnections to adjacent cells can be made from the back of the silicon sidewalls.