公开(公告)号：US5155831A

公开(公告)日：1992-10-13

申请号：US342493

申请日：1989-04-24

申请人： Philip G. Emma ,  Joshua W. Knight ,  James H. Pomerene ,  Rudolph N. Rechtschaffen ,  Frank J. Sparacio

发明人： Philip G. Emma ,  Joshua W. Knight ,  James H. Pomerene ,  Rudolph N. Rechtschaffen ,  Frank J. Sparacio

IPC分类号： G06F7/78 ,  G06F12/08 ,  G06F15/16 ,  G06F15/177

CPC分类号： G06F7/785 ,  G06F12/0804 ,  G06F12/0828

摘要： A fast queue mechanism is provided which keeps a queue of changes (i.e. store actions) issued by each processor, which queue is accessible by all processors. When any processor issues a store action to a line of memory in the queue, the old data is overwritten with the new data. If the queue does not currently have a corresponding entry, a new entry is activated. Room for the new entry is made by selecting some existing entry, either the oldest or the least recently used, to be removed. An entry that is to be removed is first used to update the line corresponding to it in main memory. After the changes held in the entry to be removed are applied to the old value of the line (from main memory) and the updated value is put back into main memory, the entry in the queue is removed by marking it "empty". When a processor accesses a line of data not in its cache, a cache miss occurs and it is necessary to fetch the line from main memory. Such fetches are monitored by the queue mechanism to see if it is holding changes to the line being fetched. If so, the changes are applied to the line coming from main memory before the line is sent to the requesting processor. After a new entry is made in the queue mechanism, other store actions to the same entry by any processor may occur and usually a number of store actions will occur to the entry before it is removed to make room for another.

公开(公告)号：US5210831A

公开(公告)日：1993-05-11

申请号：US429922

申请日：1989-10-30

申请人： Philip G. Emma ,  Joshua W. Knight ,  James H. Pomerene ,  Rudolph N. Rechtschaffen ,  Frank J. Sparacio

发明人： Philip G. Emma ,  Joshua W. Knight ,  James H. Pomerene ,  Rudolph N. Rechtschaffen ,  Frank J. Sparacio

IPC分类号： G06F9/38

CPC分类号： G06F9/3844

摘要： Methods and apparatus are described for processing branch instructions using a history based branch prediction mechanism (such as a branch history table) in combination with a data dependent branch table (DDBT), where the branch instructions can vary in both outcome and test operand location. The novel methods and apparatus are sensitive to branch mispredictions and to operand addresses used by the DDBT, to identify irrelevant DDBT entries. Irrelevant DDBT entries are identified within the prediction mechanism using state bits which, when set, indicate that: (1) a given entry in the prediction mechanism was updated by the DDBT and (2) subsequent to such update a misprediction occurred making further DDBT updates irrelevant. Once a DDBT entry is determined to be irrelevant, it is prevented from updating the prediction mechanism. The invention also provides methods and apparatus for locating and removing irrelevant entries from the DDBT. The update packet, sent by the DDBT to the history based prediction mechanism, is expanded to include the test operand address actually used by the DDBT. If the state bits indicate the update is irrelevant, then the operand address can be used to locate and delete the offending DDBT entry since the DDBT is organized based on operand addresses. Additionally, the invention provides for inhibiting creation of further DDBT entries when a Branch Wrong Guess event occurs subsequent to a DDBT update to a given prediction mechanism entry.

公开(公告)号：US4991090A

公开(公告)日：1991-02-05

申请号：US51792

申请日：1987-05-18

申请人： Philip G. Emma ,  Joshua W. Knight, III ,  James H. Pomerene ,  Rudolph N. Rechtschaffen ,  Frank J. Sparacio

发明人： Philip G. Emma ,  Joshua W. Knight, III ,  James H. Pomerene ,  Rudolph N. Rechtschaffen ,  Frank J. Sparacio

IPC分类号： G06F9/38 ,  G06F15/16 ,  G06F15/177

CPC分类号： G06F9/3814 ,  G06F9/3802 ,  G06F9/3834

摘要： Monitoring apparatus is provided to allow out-of-sequence fetching of operands while preserving the appearance of in-sequence fetching to the processor of a computer. The key elements include a stack (119) of N entries holding the addresses of the last M, where M is less than or equal to N, out-of-sequence fetches. A comparator (103) is provided for comparing addresses in the stack with a test address. This test address is supplied via an OR gate (107) as either store addresses or cross-invalidate addresses, the latter being for a multiprocessor system. The addresses in the stack that compare with the test address are set as invalid. In addition, all addresses in the stack are set as invalid on the occurrence of a cache miss or serializing instruction. Finally, a select and check entry function (113) associates an address in the stack with the instruction it represents and deletes the address from the stack when the instruction is handled in its proper sequence.

公开(公告)号：US5276882A

公开(公告)日：1994-01-04

申请号：US558998

申请日：1990-07-27

申请人： Philip G. Emma ,  Joshua W. Knight ,  James H. Pomerene ,  Rudolph N. Rechtschaffen ,  Frank J. Sparacio ,  Charles F. Webb

发明人： Philip G. Emma ,  Joshua W. Knight ,  James H. Pomerene ,  Rudolph N. Rechtschaffen ,  Frank J. Sparacio ,  Charles F. Webb

IPC分类号： G06F9/38 ,  G06F9/42

CPC分类号： G06F9/3806 ,  G06F9/30054 ,  G06F9/4426

摘要： Method and apparatus for correctly predicting an outcome of a branch instruction in a system of the type that includes a Branch History Table (BHT) and branch instructions that implement non-explicit subroutine calls and returns. Entries in the BHT have two additional stage fields including a CALL field to indicate that the branch entry corresponds to a branch that may implement a subroutine call and a PSEUDO field. The PSEUDO field represents linkage information and creates a link between a subroutine entry and a subroutine return. A target address of a successful branch instruction is used to search the BHT. The branch is known to be a subroutine return if a target quadword contains an entry prior to a target halfword that has the CALL field set. The entry with the CALL bit set is thus known to be the corresponding subroutine call, and the entry point to the subroutine is given by the target address stored within the entry. A PSEUDO entry is inserted into the BHT at the location corresponding to the entry point of the subroutine, the PSEUDO entry being designated as such by having the PSEUDO field asserted. The PSEUDO entry contains the address of the returning branch instruction in place of the target address field.

摘要翻译： 用于正确预测包括分支历史表（BHT）的类型的系统中的分支指令的结果和实现非显式子程序调用和返回的分支指令的方法和装置。 BHT中的条目具有两个附加的阶段字段，包括CALL字段，以指示分支条目对应于可以实现子程序调用的分支和PSEUDO字段。 PSEUDO字段表示链接信息，并创建子程序条目和子程序返回之间的链接。 成功的分支指令的目标地址用于搜索BHT。 如果目标四字包含有设置了CALL字段的目标半字之前的条目，则该分支被称为子程序返回。 因此，具有CALL位置位的条目是相应的子程序调用，并且子程序的入口点由存储在条目中的目标地址给出。 将PSEUDO条目插入到与子程序的入口点相对应的位置处的BHT中，PSEUDO条目被指定为通过使PSEUDO字段被断言。 PSEUDO条目包含返回分支指令的地址，代替目标地址字段。

公开(公告)号：US5291442A

公开(公告)日：1994-03-01

申请号：US606242

申请日：1990-10-31

申请人： Philip G. Emma ,  Joshua W. Knight ,  Kevin P. McAuliffe ,  James H. Pomerene ,  Rudolph N. Rechtschaffen ,  Frank J. Sparacio

发明人： Philip G. Emma ,  Joshua W. Knight ,  Kevin P. McAuliffe ,  James H. Pomerene ,  Rudolph N. Rechtschaffen ,  Frank J. Sparacio

IPC分类号： G06F12/08 ,  G06F12/06

CPC分类号： G06F12/0817

摘要： A system is provided for management of data in cache memories in a multiprocessor environment which allows portions of lines to be valid and exclusive, while other portions are valid, but not exclusive, or invalid. A processor may store into portions of a line under its exclusive control without invalidating copies of the line held in the cache memories of the other processors. The system includes at least two processors, a shared main memory and a system control element, and each processor has a corresponding cache memory, a modified line stack and a sectored line directory. The modified line stack identifies data lines which have been changed since being made resident in cache memory. It also identifies the status of change of each word within those lines. A "shared exclusive" flag in the system control element identifies each line for which portions of the line are under exclusive control of more than one processor. The sectored line directory identifies the control status and change status of individual words within a line flagged as "shared exclusive." If a line is shared exclusive, an entry for that line is recorded in the sectored line directory. For those lines with entries in the sectored line directory, a processor may store into words within its exclusive control, and fetch words within its exclusive or read-only control. Remote processors may fetch words which are held read-only by the local processor, and store into words which are marked invalid in the cache memory of the local processor.

摘要翻译： 提供了一种用于在多处理器环境中的高速缓冲存储器中的数据管理系统，其允许部分行有效和排他，而其他部分是有效的，但不是排他的或无效的。 处理器可以在其独占控制下存储在一部分行中，而不会使保持在其他处理器的高速缓冲存储器中的行的副本无效。 该系统包括至少两个处理器，共享主存储器和系统控制元件，并且每个处理器具有对应的高速缓冲存储器，修改的线路堆栈和扇区线路目录。 经修改的行堆栈标识自从驻留在高速缓冲存储器中以来已经改变的数据行。 它还标识了这些行中每个单词的变化状态。 系统控制元件中的“共享独占”标志标识线路的哪些部分在多于一个处理器的排他控制下的每一行。 分区线目录标识一个标记为“共享排他”的行内的单个单词的控制状态和状态。 如果一条线是共享的，该行的条目将被记录在该部分的行目录中。 对于那些在分区行目录中具有条目的行，处理器可以存储在其排他控制内的单词中，并在其独占或只读控制中取出单词。 远程处理器可以获取由本地处理器保持为只读的字，并且存储为在本地处理器的高速缓冲存储器中被标记为无效的字。

公开(公告)号：US5197139A

公开(公告)日：1993-03-23

申请号：US505198

申请日：1990-04-05

申请人： Philip G. Emma ,  Joshua W. Knight ,  James H. Pomerene ,  Thomas R. Puzak ,  Rudolph N. Rechtschaffen ,  Frank J. Sparacio

发明人： Philip G. Emma ,  Joshua W. Knight ,  James H. Pomerene ,  Thomas R. Puzak ,  Rudolph N. Rechtschaffen ,  Frank J. Sparacio

IPC分类号： G06F12/08

CPC分类号： G06F12/0817

摘要： A store through cache environment managed exclusively grants exclusivity on a large granularity basis. A cross-invalidate is realized for all changed lines via a single transmission when exclusivity is released. A dynamic table that operates in conjunction with a directory look-aside table (DLAT) determines a number of pages that can be held exclusive simultaneously. For adequate operating speed, the special table must be either fully associative or at least set associative. Alternatively, the table can be incorporated into the DLAT. Each DLAT entry is also extended to include a set of "resident" bits and a "valid nonresident" bit. When exclusively is released, the set of local change bits is broadcast to all processors. Upon receipt of such broadcast, the appropriate action is to change the "valid nonresident" indication to read-only and to clear residence bits whose corresponding local change bit is set.

公开(公告)号：US4943908A

公开(公告)日：1990-07-24

申请号：US128008

申请日：1987-12-02

申请人： Philip G. Emma ,  Joshua W. Knight, III ,  James H. Pomerene ,  Rudolph N. Rechtschaffen ,  Frank J. Sparacio

发明人： Philip G. Emma ,  Joshua W. Knight, III ,  James H. Pomerene ,  Rudolph N. Rechtschaffen ,  Frank J. Sparacio

IPC分类号： G06F12/08 ,  G06F9/38

CPC分类号： G06F9/3806 ,  G06F12/0862

摘要： Apparatus for fetching instructions in a computing system. A broadband branch history table is organized by cache line. The broadband branch history table determines from the history of branches the next cache line to be referenced and uses that information for prefetching lines into the cache.

公开(公告)号：US5297281A

公开(公告)日：1994-03-22

申请号：US836193

申请日：1992-02-13

申请人： Philip G. Emma ,  Joshua W. Knight ,  James H. Pomerene ,  Rudolph N. Rechtschaffen ,  Frank J. Sparacio

发明人： Philip G. Emma ,  Joshua W. Knight ,  James H. Pomerene ,  Rudolph N. Rechtschaffen ,  Frank J. Sparacio

IPC分类号： G06F9/38 ,  G06F9/28

CPC分类号： G06F9/3844 ,  G06F9/3853 ,  G06F9/3885

摘要： A digital computer includes a main and an auxiliary pipeline processor which are configured to concurrently execute contiguous groups of instructions taken from a single instruction sequence. The instructions in a sequence may be divided into groups by using either taken-branch instructions or certain instructions which may change the contents of the general purpose registers as group delimiters. Both methods of grouping the instructions use a branch history table to predict the sequence in which the instructions will be executed.

摘要翻译： 数字计算机包括主和辅助流水线处理器，其被配置为同时执行从单个指令序列获取的连续的指令组。 序列中的指令可以通过使用分支指令或某些指令来划分成组，这些指令可以将通用寄存器的内容改变为分组分隔符。 分组指令的两种方法都使用分支历史表来预测指令执行的顺序。

公开(公告)号：US4763245A

公开(公告)日：1988-08-09

申请号：US793057

申请日：1985-10-30

申请人： Philip G. Emma ,  James H. Pomerene ,  Gururaj S. Rao ,  Rudolph N. Rechtschaffen ,  Howard E. Sachar ,  Frank J. Sparacio

发明人： Philip G. Emma ,  James H. Pomerene ,  Gururaj S. Rao ,  Rudolph N. Rechtschaffen ,  Howard E. Sachar ,  Frank J. Sparacio

IPC分类号： G06F9/38 ,  G06F9/34

CPC分类号： G06F9/3848

摘要： A data-dependent branch table is a mechanism that is sensitive to operands that will be tested in order to determine branch action outcomes. The data dependent branch table operates in conjunction with a branch history table to anticipate those instances where the branch history table will make an erroneous prediction, and corrects the branch history table prior to the time that the actual prediction is made.

摘要翻译： 数据相关的分支表是对要进行测试的操作数敏感的机制，以确定分支行动结果。 数据相关分支表与分支历史表一起工作以预测分支历史表将作出错误预测的那些实例，并且在进行实际预测的时间之前校正分支历史表。

公开(公告)号：US4991080A

公开(公告)日：1991-02-05

申请号：US839312

申请日：1986-03-13

申请人： Philip G. Emma ,  James H. Pomerene ,  Rudolph N. Rechtschaffen ,  Frank J. Sparacio

发明人： Philip G. Emma ,  James H. Pomerene ,  Rudolph N. Rechtschaffen ,  Frank J. Sparacio

IPC分类号： G06F9/38

CPC分类号： G06F9/3877 ,  G06F9/3804 ,  G06F9/3844

摘要： In an approach to reducing delays resulting from resolution of conditional branch instructions, such instructions are pre-executed in a coprocessor which precedes a pipeline processor and prepared an instruction stream for input to the pipeline processor. Because of this pre-execution, the input instruction stream has fewer conditional branches for the pipeline processor to resolve. Also, the coprocessor may handle address generation interlock situations which also cause execution delays in the pipeline processor.

摘要翻译： 在减少由条件分支指令的解决引起的延迟的方法中，这种指令在流水线处理器之前的协处理器中预先执行，并且准备了用于输入到流水线处理器的指令流。 由于这种预执行，输入指令流具有较少的条件分支以供流水线处理器解决。 此外，协处理器可以处理也导致流水线处理器中的执行延迟的地址生成互锁状况。