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    Dual-port SRAM in a programmable logic device
    1.
    发明授权
    Dual-port SRAM in a programmable logic device 有权
    可编程逻辑器件中的双端口SRAM

    公开(公告)号：US06661733B1

    公开(公告)日：2003-12-09

    申请号：US09883087

    申请日：2001-06-15

    申请人： Philip Y. Pan ,  Chiakang Sung ,  Joseph Huang ,  Bonnie Wang ,  Khai Nguyen ,  Xiaobao Wang ,  Gopinath Rangan ,  In Whan Kim ,  Yan Chong

    发明人： Philip Y. Pan ,  Chiakang Sung ,  Joseph Huang ,  Bonnie Wang ,  Khai Nguyen ,  Xiaobao Wang ,  Gopinath Rangan ,  In Whan Kim ,  Yan Chong

    IPC分类号： G11C800

    CPC分类号： H03K19/1776 ,  G11C8/16

    摘要： Methods and apparatus for a dual-port SRAM in a programmable logic device. One embodiment provides a programmable logic integrated circuit including a dual-port memory. The memory includes a plurality of memory storage cells, and each memory storage cell has a memory cell having a first node and a second node, a first series of devices connected between a first data line and the first node of the memory cell, and a second series of devices connected between a second data line and the second node of the memory cell. A read cell is connected to the second node of the memory cell. A word line is connected to a first device in the first series of devices, a second device in the second series of devices, and the read cell.

    摘要翻译： 可编程逻辑器件中双端口SRAM的方法和装置。 一个实施例提供了包括双端口存储器的可编程逻辑集成电路。 存储器包括多个存储器存储单元，并且每个存储器存储单元具有具有第一节点和第二节点的存储单元，连接在第一数据线和存储器单元的第一节点之间的第一系列器件，以及 连接在第二数据线和存储器单元的第二节点之间的第二系列器件。 读单元连接到存储单元的第二节点。 字线连接到第一系列设备中的第一设备，第二系列设备中的第二设备和读取单元。

    Configurable decoder for addressing a memory
    2.
    发明授权
    Configurable decoder for addressing a memory 有权
    用于寻址存储器的可配置解码器

    公开(公告)号：US06747903B1

    公开(公告)日：2004-06-08

    申请号：US10046939

    申请日：2002-01-14

    申请人： Philip Y. Pan ,  Chiakang Sung ,  Joseph Huang ,  Bonnie Wang ,  Khai Nguyen ,  Xiaobao Wang ,  Gopinath Rangan ,  In Whan Kim ,  Yan Chong ,  Tzung-Chin Chang

    发明人： Philip Y. Pan ,  Chiakang Sung ,  Joseph Huang ,  Bonnie Wang ,  Khai Nguyen ,  Xiaobao Wang ,  Gopinath Rangan ,  In Whan Kim ,  Yan Chong ,  Tzung-Chin Chang

    IPC分类号： G11C700

    CPC分类号： H03K19/1776 ,  G11C8/16

    摘要： Methods and apparatus for decoding addresses in a memory to provide mixed input and output data widths. A method includes receiving an address portion comprising a first number of bits. A second number of bits of the address portion are blocked, where the second number is less than the first number. A third number of bits are not blocked, and the third number plus the second number equal the first number. The third number of bits are decoded and a fourth number of memory cells are selected. The fourth number is equal to two to the power of the second number. A fourth number of data bits are received and multiplexed to the selected memory cells. The data bits are written to the selected memory cells.

    摘要翻译： 用于解码存储器中的地址以提供混合的输入和输出数据宽度的方法和装置。 一种方法包括接收包括第一位数的地址部分。 地址部分的第二位数被阻塞，其中第二个数字小于第一个数字。 第三个位数不被阻塞，第三个数字加上第二个数字等于第一个数字。 第三位数被解码，并且选择第四数量的存储单元。 第四个数字等于第二个数字的两倍。 接收第四数量的数据位并将其多路复用到选择的存储单元。 数据位被写入选定的存储单元。

    Schmitt trigger circuit with adjustable trip point voltages
    4.
    发明授权
    Schmitt trigger circuit with adjustable trip point voltages 有权
    施密特触发电路具有可调跳闸点电压

    公开(公告)号：US06870413B1

    公开(公告)日：2005-03-22

    申请号：US10017933

    申请日：2001-12-14

    申请人： Tzung-Chin Chang ,  Chiakang Sung ,  Khai Nguyen ,  Joseph Huang ,  Bonnie Wang ,  Yan Chong ,  Xiaobao Wang ,  Philip Pan ,  Gopinath Rangan ,  In Whan Kim

    发明人： Tzung-Chin Chang ,  Chiakang Sung ,  Khai Nguyen ,  Joseph Huang ,  Bonnie Wang ,  Yan Chong ,  Xiaobao Wang ,  Philip Pan ,  Gopinath Rangan ,  In Whan Kim

    IPC分类号： H03K3/3565 ,  H03K3/012

    CPC分类号： H03K3/3565

    摘要： A Schmitt trigger circuit has an adjustable hysteresis characteristic by providing a plurality of feedback circuits that differently affect at least one, and preferably both, of the circuit's upper trip point level and lower trip point level. The upper trip point level can be adjusted by selecting a desired feedback circuit from a first set of feedback circuits, and/or the lower trip point level can be adjusted by selecting a desired feedback circuit from a second set of feedback circuits. Feedback circuit selection is achieved by one or more control signals that may be programmable. The hysteresis characteristic can be adjusted to meet desired noise margin, delay, and input recognition criteria at different VCC levels. The Schmitt trigger circuit may be a CMOS Schmitt trigger with two input stage NMOS, two input stage PMOS transistors, a first set of NMOS feedback circuits, and a second set of PMOS feedback circuits.

    摘要翻译： 施密特触发电路具有可调滞后特性，通过提供多个反馈电路，其不同地影响电路的上跳点电平和较低跳变点电平的至少一个，优选两者。 可以通过从第一组反馈电路中选择所需的反馈电路来调整上跳点电平，和/或可以通过从第二组反馈电路中选择所需的反馈电路来调整下跳变点电平。 反馈电路选择由一个或多个可编程的控制信号来实现。 可以调节滞后特性，以满足不同VCC电平下的所需噪声容限，延迟和输入识别准则。 施密特触发电路可以是具有两个输入级NMOS，两个输入级PMOS晶体管，第一组NMOS反馈电路组和第二组PMOS反馈电路的CMOS施密特触发器。

    On/off reference voltage switch for multiple I/O standards
    8.
    发明授权
    On/off reference voltage switch for multiple I/O standards 有权
    用于多个I / O标准的开/关参考电压开关

    公开(公告)号：US06911860B1

    公开(公告)日：2005-06-28

    申请号：US10037716

    申请日：2001-11-09

    申请人： Xiaobao Wang ,  Chiakang Sung ,  Khai Nguyen ,  Joseph Huang ,  Bonnie Wang ,  Philip Pan ,  Yan Chong ,  In Whan Kim ,  Gopinath Rangan ,  Tzung-Chin Chang

    发明人： Xiaobao Wang ,  Chiakang Sung ,  Khai Nguyen ,  Joseph Huang ,  Bonnie Wang ,  Philip Pan ,  Yan Chong ,  In Whan Kim ,  Gopinath Rangan ,  Tzung-Chin Chang

    IPC分类号： H03K17/35

    CPC分类号： H03K17/6871 ,  H03K3/356113 ,  H03K17/063

    摘要： A switch circuit selectively provides a reference voltage, needed in some I/O standards, to a logic device. The circuit receives a dedicated power supply that is different from the device's I/O supply. It may also include a level shifting circuit for converting a master control signal having a logic level determined by a first supply to a first control signal having a logic level determined by the dedicated supply. The switch circuit also includes a transmission switch that passes the reference voltage to an output in response to at least the first control signal. The transmission switch may be a CMOS transmission gate with at least one NMOS transistor controlled by the first control signal in parallel with at least one PMOS transistor controlled by a second control signal, complementary to the first. The second control signal may be generated by another level shifting circuit and have a logic level determined by the I/O supply.

    摘要翻译： 开关电路选择性地将某些I / O标准所需的参考电压提供给逻辑器件。 该电路接收与设备的I / O电源不同的专用电源。 其还可以包括电平移位电路，用于将具有由第一电源确定的逻辑电平的主控制信号转换成具有由专用电源确定的逻辑电平的第一控制信号。 开关电路还包括传输开关，其响应于至少第一控制信号将参考电压传递到输出。 传输开关可以是CMOS传输门，其中至少一个NMOS晶体管由第一控制信号控制，与由与第一控制信号互补的第二控制信号控制的至少一个PMOS晶体管并联。 第二控制信号可以由另一电平移位电路产生并具有由I / O电源确定的逻辑电平。