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1.发明授权Method of manufacturing a semiconductor device and semiconductor device obtained by means of said method 有权通过所述方法获得的制造半导体器件和半导体器件的方法公开(公告)号：US07825011B2
公开(公告)日：2010-11-02
申请号：US11913255
申请日：2006-04-28
CPC分类号： H01L29/1054 , H01L21/76264 , H01L29/66575 , H01L29/78
摘要： The invention relates to a method of manufacturing a semiconductor device (10) comprising a substrate (11) and a semiconductor body (12) in which at least one semiconductor element (1) is formed, wherein on the substrate (11) a semiconductor layer (2) is formed comprising a mixed crystal of silicon and germanium, further called the silicon-germanium layer (2) and having a lower surface close to the substrate (11) and an upper surface more remote from the substrate (11), and wherein the silicon-germanium layer (2) is subjected to an oxidizing treatment at a surface of the silicon-germanium layer (2) while the other surface of the silicon-germanium layer (2) is protected against the oxidizing treatment by a blocking layer (3). According to the invention, the blocking layer (3) is formed on the upper surface of the silicon-germanium layer (2), a cavity (5) is formed in the semiconductor body below the silicon-germanium layer (2) and the lower surface of the silicon-germanium layer (2) is subjected to the oxidizing treatment through the cavity (2). In this way, a device 10 may be obtained in which the surface of the silicon-germanium layer (2) after the oxidizing treatment does not suffer from roughening and/or germanium pile up. This enables e.g. to manufacture in particular a MOSFET on top of or in the silicon-germanium layer (2) with excellent properties and high yield.
摘要翻译： 本发明涉及一种制造半导体器件（10）的方法，该半导体器件（10）包括其中形成有至少一个半导体元件（1）的衬底（11）和半导体本体（12），其中在衬底（11）上形成半导体层 （2）形成，包括硅和锗的混合晶体，进一步称为硅 - 锗层（2），并且具有靠近基板（11）的下表面和更远离基板（11）的上表面，以及 其中所述硅 - 锗层（2）在所述硅 - 锗层（2）的表面进行氧化处理，同时所述硅 - 锗层（2）的另一个表面被阻挡层 （3）。 根据本发明，在硅 - 锗层（2）的上表面上形成阻挡层（3），在硅 - 锗层（2）下面的半导体本体中形成空腔（5），下层 硅 - 锗层（2）的表面通过空腔（2）进行氧化处理。 以这种方式，可以获得其中氧化处理后的硅 - 锗层（2）的表面不会遭受粗糙化和/或锗堆积的器件10。 这使得例如。 特别是在硅 - 锗层（2）之上或之上制造具有优异性能和高产率的MOSFET。
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公开(公告)号：US20100237434A1
公开(公告)日：2010-09-23
申请号：US11993296
申请日：2006-06-22
CPC分类号： H01L29/7378 , B82Y20/00 , H01L21/743 , H01L21/76229 , H01L21/8222 , H01L21/8249 , H01L29/1087 , H01L29/41708 , H01L29/42384 , H01L29/66242 , H01L29/78 , H01L29/78645 , H01L29/78696 , H01L31/035236 , H01L31/1812 , Y02E10/50
摘要： The invention relates to a semiconductor device (10) with a substrate (11) and a semiconductor body (12) of silicon which comprises an active region (A) with a transistor (T) and a passive region (P) surrounding the active region (A) and which is provided with a buried conducting region (1) of a metallic material that is connected to a conductive region (2) of a metallic material sunken from the surface of the semiconductor body (12), by which the buried conductive region (1) is made electrically connectable at the surface of the semiconductor body (12). According to the invention, the buried conducting region (1) is made at the location of the active region (A) of the semiconductor body (12). In this way, a very low buried resistance can be locally created in the active region (A) in the semiconductor body (12), using a metallic material that has completely different crystallographic properties from the surrounding silicon. This is made possible by using a method according to the invention. Such a buried low resistance offers substantial advantages both for a bipolar transistor and for a MOS transistor.
摘要翻译： 本发明涉及具有衬底（11）和硅的半导体本体（12）的半导体器件（10），其包括具有晶体管（T）的有源区（A）和围绕有源区的无源区（P） （A），并且设置有金属材料的埋入导电区域（1），所述埋入导电区域连接到从所述半导体主体（12）的表面凹陷的金属材料的导电区域（2），所述埋入导电区域 区域（1）在半导体本体（12）的表面处可电连接。 根据本发明，在半导体本体（12）的有源区（A）的位置处形成掩埋导电区（1）。 以这种方式，可以使用与周围的硅具有完全不同的晶体学特性的金属材料，在半导体本体（12）的有源区（A）中局部地产生非常低的掩埋电阻。 这可以通过使用根据本发明的方法来实现。 这种埋下的低电阻为双极晶体管和MOS晶体管提供了显着的优点。
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3.发明授权Semiconductor device with low buried resistance and method of manufacturing such a device 有权具有低掩埋电阻的半导体器件及其制造方法公开(公告)号：US07956399B2
公开(公告)日：2011-06-07
申请号：US11993296
申请日：2006-06-22
IPC分类号： H01L23/485
CPC分类号： H01L29/7378 , B82Y20/00 , H01L21/743 , H01L21/76229 , H01L21/8222 , H01L21/8249 , H01L29/1087 , H01L29/41708 , H01L29/42384 , H01L29/66242 , H01L29/78 , H01L29/78645 , H01L29/78696 , H01L31/035236 , H01L31/1812 , Y02E10/50
摘要： The invention relates to a semiconductor device (10) with a substrate (11) and a semiconductor body (12) of silicon which comprises an active region (A) with a transistor (T) and a passive region (P) surrounding the active region (A) and which is provided with a buried conducting region (1) of a metallic material that is connected to a conductive region (2) of a metallic material sunken from the surface of the semiconductor body (12), by which the buried conductive region (1) is made electrically connectable at the surface of the semiconductor body (12). According to the invention, the buried conducting region (1) is made at the location of the active region (A) of the semiconductor body (12). In this way, a very low buried resistance can be locally created in the active region (A) in the semiconductor body (12), using a metallic material that has completely different crystallographic properties from the surrounding silicon. This is made possible by using a method according to the invention. Such a buried low resistance offers substantial advantages both for a bipolar transistor and for a MOS transistor.
摘要翻译： 本发明涉及具有衬底（11）和硅的半导体本体（12）的半导体器件（10），其包括具有晶体管（T）的有源区（A）和围绕有源区的无源区（P） （A），并且设置有金属材料的埋入导电区域（1），所述埋入导电区域连接到从所述半导体主体（12）的表面凹陷的金属材料的导电区域（2），所述埋入导电区域 区域（1）在半导体本体（12）的表面处可电连接。 根据本发明，在半导体本体（12）的有源区（A）的位置处形成掩埋导电区（1）。 以这种方式，可以使用与周围的硅具有完全不同的晶体学特性的金属材料，在半导体本体（12）的有源区（A）中局部地产生非常低的掩埋电阻。 这可以通过使用根据本发明的方法来实现。 这种埋下的低电阻为双极晶体管和MOS晶体管提供了显着的优点。
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4.发明申请METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE OBTAINED BY MEANS OF SAID METHOD 有权制造半导体器件的方法和通过方法获得的半导体器件公开(公告)号：US20090072351A1
公开(公告)日：2009-03-19
申请号：US11913255
申请日：2006-04-28
CPC分类号： H01L29/1054 , H01L21/76264 , H01L29/66575 , H01L29/78
摘要： The invention relates to a method of manufacturing a semiconductor device (10) comprising a substrate (11) and a semiconductor body (12) in which at least one semiconductor element (1) is formed, wherein on the substrate (11) a semiconductor layer (2) is formed comprising a mixed crystal of silicon and germanium, further called the silicon-germanium layer (2) and having a lower surface close to the substrate (11) and an upper surface more remote from the substrate (11), and wherein the silicon-germanium layer (2) is subjected to an oxidizing treatment at a surface of the silicon-germanium layer (2) while the other surface of the silicon-germanium layer (2) is protected against the oxidizing treatment by a blocking layer (3). According to the invention, the blocking layer (3) is formed on the upper surface of the silicon-germanium layer (2), a cavity (5) is formed in the semiconductor body below the silicon-germanium layer (2) and the lower surface of the silicon-germanium layer (2) is subjected to the oxidizing treatment through the cavity (2). In this way, a device 10 may be obtained in which the surface of the silicon-germanium layer (2) after the oxidizing treatment does not suffer from roughening and/or germanium pile up. This enables e.g. to manufacture in particular a MOSFET on top of or in the silicon-germanium layer (2) with excellent properties and high yield.
摘要翻译： 本发明涉及一种制造半导体器件（10）的方法，该半导体器件（10）包括其中形成有至少一个半导体元件（1）的衬底（11）和半导体本体（12），其中在衬底（11）上形成半导体层 （2）形成，包括硅和锗的混合晶体，进一步称为硅 - 锗层（2），并且具有靠近基板（11）的下表面和更远离基板（11）的上表面，以及 其中所述硅 - 锗层（2）在所述硅 - 锗层（2）的表面进行氧化处理，同时所述硅 - 锗层（2）的另一个表面被阻挡层 （3）。 根据本发明，在硅 - 锗层（2）的上表面上形成阻挡层（3），在硅 - 锗层（2）下面的半导体本体中形成空腔（5），下层 硅 - 锗层（2）的表面通过空腔（2）进行氧化处理。 以这种方式，可以获得其中氧化处理后的硅 - 锗层（2）的表面不会遭受粗糙化和/或锗堆积的器件10。 这使得例如。 特别是在硅 - 锗层（2）之上或之上制造具有优异性能和高产率的MOSFET。
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公开(公告)号：US08592228B2
公开(公告)日：2013-11-26
申请号：US12515590
申请日：2007-11-15
IPC分类号： H01L21/00
CPC分类号： B81C1/00293 , B81B2201/0271 , B81C2203/0145
摘要： A method of manufacturing a structure (1100), the method comprising forming a cap element (401) on a substrate (101), removing material (103) of the substrate (101) below the cap element (401) to thereby form a gap (802) between the cap element (401) and the substrate (101), and rearranging material of the cap element (401) and/or of the substrate (101) to thereby merge the cap element (401) and the substrate (101) to bridge the gap (802).
摘要翻译： 一种制造结构（1100）的方法，所述方法包括在基板（101）上形成盖元件（401），在盖元件（401）下方去除基板（101）的材料（103），从而形成间隙 （401）和基板（101）之间的盖（802）和盖元件（401）和/或基板（101）的重新排列材料，从而合并盖元件（401）和基板（101） ）弥合差距（802）。
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6.发明授权Method of manufacturing heterojunction bipolar transistor and heterojunction bipolar transistor 有权异质结双极晶体管和异质结双极晶体管的制造方法公开(公告)号：US08524551B2
公开(公告)日：2013-09-03
申请号：US13547067
申请日：2012-07-12
申请人： Philippe Meunier-Beillard , Johannes Josephus Theodorus Marinus Donkers , Hans Mertens , Tony Vanhoucke
发明人： Philippe Meunier-Beillard , Johannes Josephus Theodorus Marinus Donkers , Hans Mertens , Tony Vanhoucke
IPC分类号： H01L21/337
CPC分类号： H01L29/66242 , H01L29/1004 , H01L29/7378
摘要： A method of forming a heterojunction bipolar transistor by depositing a first stack comprising an polysilicon layer and a sacrificial layer on a mono-crystalline silicon substrate surface; patterning that stack to form a trench extending to the substrate; depositing a silicon layer over the resultant structure; depositing a silicon-germanium-carbon layer over the resultant structure; selectively removing the silicon-germanium-carbon layer from the sidewalls of the trench; depositing a boron-doped silicon-germanium-carbon layer over the resultant structure; depositing a further silicon-germanium-carbon layer over the resultant structure; depositing a boron-doped further silicon layer over the resultant structure; forming dielectric spacers on the trench sidewalls; filling the trench with emitter material; exposing polysilicon regions outside the trench side walls by selectively removing the sacrificial layer; implanting boron impurities into the exposed polysilicon regions to define base implants; and exposing the resultant structure to a thermal budget for annealing the boron impurities.
摘要翻译： 一种通过在单晶硅衬底表面上沉积包括多晶硅层和牺牲层的第一堆叠来形成异质结双极晶体管的方法; 图案化该叠层以形成延伸到衬底的沟槽; 在所得结构上沉积硅层; 在所得结构上沉积硅 - 锗 - 碳层; 从沟槽的侧壁选择性地去除硅 - 锗 - 碳层; 在所得结构上沉积硼掺杂的硅 - 锗 - 碳层; 在所得结构上沉积另外的硅 - 锗 - 碳层; 在所得结构上沉积硼掺杂的另外的硅层; 在沟槽侧壁上形成电介质间隔物; 用发射体材料填充沟槽; 通过选择性地去除牺牲层来暴露沟槽侧壁外的多晶硅区域; 将硼杂质注入暴露的多晶硅区域以限定基底植入物; 并将所得结构暴露于用于退火硼杂质的热预算。
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公开(公告)号：US08481365B2
公开(公告)日：2013-07-09
申请号：US12995100
申请日：2009-05-19
CPC分类号： B81C1/00293 , B81C2203/0145
摘要： A method of manufacturing a MEMS device comprises forming a MEMS device element (14). A sacrificial layer (20) is provided over the device element and a package cover layer (22) is provided over the sacrificial layer. The sacrificial layer is removed using at least one opening (22) in the cover layer and the at least one opening (24) is sealed by an anneal process.
摘要翻译： 制造MEMS器件的方法包括形成MEMS器件元件（14）。 牺牲层（20）设置在器件元件上方，并且封装覆盖层（22）设置在牺牲层上。 使用覆盖层中的至少一个开口（22）去除牺牲层，并且通过退火工艺密封至少一个开口（24）。
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公开(公告)号：US20110215417A1
公开(公告)日：2011-09-08
申请号：US12918542
申请日：2009-02-26
申请人： Philippe Meunier-Beillard , Mark C.J.C.M. Kramer , Johannes J.T.M. Donkers , Guillaume Boccardi
发明人： Philippe Meunier-Beillard , Mark C.J.C.M. Kramer , Johannes J.T.M. Donkers , Guillaume Boccardi
IPC分类号： H01L27/06 , H01L21/8249
CPC分类号： H01L21/8249 , H01L27/0623 , H01L29/0649 , H01L29/0821 , H01L29/1004 , H01L29/165 , H01L29/42304 , H01L29/456 , H01L29/66242 , H01L29/7378
摘要： A semiconductor device (10) comprising a bipolar transistor and a field effect transistor within a semiconductor body (1) comprising a projecting mesa (5) within which are at least a portion of a collector region (22d and 22e) and a base region (33d) of the bipolar transistor. The bipolar transistor is provided with a first insulating cavity (92) provided in the collector region (22d and 22e). The base region (33d) is narrower in the plane of the substrate than the collector region (22d and 22e) due to a second insulating cavity (94) provided around the base region (33d) and between the collector region (22d and 22e) and the emitter region (4). By blocking diffusion from the base region the first insulating cavity (92) provides a reduction in the base collector capacitance and can be described as defining the base contact.
摘要翻译： 一种半导体器件（10），包括半导体本体（1）内的双极晶体管和场效应晶体管，所述半导体本体（1）包括突出台面（5），所述突出台面（5）中至少一部分为集电极区域（22d和22e）和基极区域 33d）。 双极晶体管设置有设置在集电区域（22d和22e）中的第一绝缘腔（92）。 基极区域（33d）由于设置在基极区域（33d）周围的第二绝缘腔（94d）和集电极区域（22d〜22e）之间，在基板的平面内比集电体区域（22d，22e）窄， 和发射极区域（4）。 通过阻挡来自基极区域的扩散，第一绝缘腔（92）提供基极集电极电容的减小并且可以被描述为限定基极触点。
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公开(公告)号：US20100052081A1
公开(公告)日：2010-03-04
申请号：US12515590
申请日：2007-11-15
IPC分类号： H01L29/84 , H01L21/306
CPC分类号： B81C1/00293 , B81B2201/0271 , B81C2203/0145
摘要： A method of manufacturing a structure (1100), the method comprising forming a cap element (401) on a substrate (101), removing material (103) of the substrate (101) below the cap element (401) to thereby form a gap (802) between the cap element (401) and the substrate (101), and rearranging material of the cap element (401) and/or of the substrate (101) to thereby merge the cap element (401) and the substrate (101) to bridge the gap (802).
摘要翻译： 一种制造结构（1100）的方法，所述方法包括在基板（101）上形成盖元件（401），在盖元件（401）下方去除基板（101）的材料（103），从而形成间隙 （401）和基板（101）之间的盖（802）和盖元件（401）和/或基板（101）的重新排列材料，从而合并盖元件（401）和基板（101） ）弥合差距（802）。
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公开(公告)号：US20070222019A1
公开(公告)日：2007-09-27
申请号：US10594487
申请日：2005-03-29
IPC分类号： H01L29/36
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/405 , H01L29/407 , H01L29/408 , H01L29/66712 , H01L29/7811
摘要： Consistent with an example embodiment, a reduced surface field effect type (RESURF) semiconductor device is manufactured having a drift region over a drain region. Trenches are formed through openings in mask. A trench insulating layer is deposited on the sidewalls and base of the trenches followed by an overetching step to remove the trench insulating layer from the base of the trenches as well as the top of the sidewalls of the trenches adjacent to the first major surface leaving exposed silicon at the top of the sidewalls of the trench and the base of the trenches. Silicon is selectively grown plugging the trenches with silicon plug (18) leaving void.
摘要翻译： 与示例性实施例一致，制造了在漏极区域上具有漂移区域的减小的表面场效应型（RESURF）半导体器件。 通过面罩中的开口形成沟槽。 沟槽绝缘层沉积在沟槽的侧壁和基底上，随后进行过蚀刻步骤以从沟槽的底部除去沟槽绝缘层以及与第一主表面相邻的沟槽的侧壁的顶部，留下暴露的 在沟槽的侧壁的顶部和沟槽的底部的硅。 硅被选择性地生长，用硅塞（18）堵塞沟槽，留下空隙。
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