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    REDUCTION OF FORMING VOLTAGE IN SEMICONDUCTOR DEVICES
    1.
    发明申请
    REDUCTION OF FORMING VOLTAGE IN SEMICONDUCTOR DEVICES 有权
    减少半导体器件中的成形电压

    公开(公告)号：US20090272962A1

    公开(公告)日：2009-11-05

    申请号：US12391784

    申请日：2009-02-24

    申请人： Pragati Kumar ,  Yun Wang ,  Prashant Phatak ,  Tony P. Chiang

    发明人： Pragati Kumar ,  Yun Wang ,  Prashant Phatak ,  Tony P. Chiang

    IPC分类号： H01L45/00 ,  H01L21/28

    CPC分类号： H01L45/146 ,  G11C13/0002 ,  G11C2013/0083 ,  G11C2213/51 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1625 ,  H01L45/1641

    摘要： This disclosure provides a nonvolatile memory device and related methods of manufacture and operation. The device may include one or more resistive random access memory (RRAM) that use techniques to provide a memory device with more predictable operation. In particular, forming voltage required by particular designs may be reduced through the use of a barrier layer, a reverse polarity forming voltage pulse, a forming voltage pulse where electrons are injected from a lower work function electrode, or through the use of an anneal in a reducing environment. One or more of these techniques may be applied, depending on desired application and results.

    摘要翻译： 本公开提供了一种非易失性存储器件及相关的制造和操作方法。 该设备可以包括使用技术来向存储器设备提供更可预测的操作的一个或多个电阻随机存取存储器（RRAM）。 特别地，可以通过使用阻挡层，反极性形成电压脉冲，形成电压脉冲（其中电子从下功能电极注入）或通过使用退火进行退火来降低特定设计所需的形成电压 减少环境。 可以根据期望的应用和结果应用这些技术中的一种或多种。

    ALD processing techniques for forming non-volatile resistive-switching memories
    3.
    发明授权
    ALD processing techniques for forming non-volatile resistive-switching memories 有权
    用于形成非易失性电阻式切换存储器的ALD处理技术

    公开(公告)号：US08481338B2

    公开(公告)日：2013-07-09

    申请号：US13184335

    申请日：2011-07-15

    申请人： Nobi Fuchigami ,  Pragati Kumar ,  Prashant Phatak

    发明人： Nobi Fuchigami ,  Pragati Kumar ,  Prashant Phatak

    IPC分类号： H01L21/00

    CPC分类号： H01L45/146 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1616

    摘要： ALD processing techniques for forming non-volatile resistive-switching memories are described. In one embodiment, a method includes forming a first electrode on a substrate, maintaining a pedestal temperature for an atomic layer deposition (ALD) process of less than 100° Celsius, forming at least one metal oxide layer over the first electrode, wherein the forming the at least one metal oxide layer is performed using the ALD process using a purge duration of less than 20 seconds, and forming a second electrode over the at least one metal oxide layer.

    摘要翻译： 描述用于形成非易失性电阻式切换存储器的ALD处理技术。 在一个实施例中，一种方法包括在衬底上形成第一电极，保持小于100℃的原子层沉积（ALD）工艺的基座温度，在第一电极上形成至少一个金属氧化物层，其中形成 所述至少一个金属氧化物层使用ALD工艺，使用小于20秒的吹扫持续时间，并在所述至少一个金属氧化物层上形成第二电极。

    Closed loop sputtering controlled to enhance electrical characteristics in deposited layer
    4.
    发明申请
    Closed loop sputtering controlled to enhance electrical characteristics in deposited layer 有权
    控制闭环溅射以增强沉积层中的电特性

    公开(公告)号：US20120256155A1

    公开(公告)日：2012-10-11

    申请号：US13249631

    申请日：2011-09-30

    申请人： Wayne French ,  Pragati Kumar ,  Prashant Phatak ,  Tony Chiang

    发明人： Wayne French ,  Pragati Kumar ,  Prashant Phatak ,  Tony Chiang

    IPC分类号： H01L45/00

    CPC分类号： C23C14/083 ,  C23C14/0042 ,  C23C14/54 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/165

    摘要： This disclosure provides a method of fabricating a semiconductor device layer and an associated memory cell. Empirical data may be used to generate a hysteresis curve associated with deposition for a metal-insulator-metal structure, with curve measurements reflecting variance of an electrical property as a function of cathode voltage used during a sputtering process. By generating at least one voltage level to be used during the sputtering process, where the voltage reflects a suitable value for the electrical property from among the values obtainable in mixed-mode deposition, a semiconductor device layer may be produced with improved characteristics and durability. A multistable memory cell or array of such cells manufactured according to this process can, for a set of given materials, be fabricated to have minimal leakage or “off” current characteristics (Ileak or Ioff, respectively) or a maximum ratio of “on” current to “off” current (Ion/Ioff).

    摘要翻译： 本公开提供了制造半导体器件层和相关联的存储单元的方法。 经验数据可用于产生与金属 - 绝缘体 - 金属结构的沉积相关联的滞后曲线，其中曲线测量反映作为在溅射过程中使用的阴极电压的函数的电特性的变化。 通过在溅射过程中产生要使用的至少一个电压电平，其中电压从混合模式沉积中可获得的值中反映适合的电特性值，可以制造具有改进的特性和耐久性的半导体器件层。 对于一组给定材料制造的这种电池的多电平存储器单元或阵列可以被制造成具有最小的泄漏或截止电流特性（分别为Ileak或Ioff）或电流与截止电流的最大比率 （Ion / Ioff）。

    ALD PROCESSING TECHNIQUES FOR FORMING NON-VOLATILE RESISTIVE-SWITCHING MEMORIES
    6.
    发明申请
    ALD PROCESSING TECHNIQUES FOR FORMING NON-VOLATILE RESISTIVE-SWITCHING MEMORIES 有权
    用于形成非易失性电阻开关存储器的ALD处理技术

    公开(公告)号：US20090302296A1

    公开(公告)日：2009-12-10

    申请号：US12478680

    申请日：2009-06-04

    申请人： Nobi Fuchigami ,  Pragati Kumar ,  Prashant Phatak

    发明人： Nobi Fuchigami ,  Pragati Kumar ,  Prashant Phatak

    IPC分类号： H01L47/00 ,  H01L21/16

    CPC分类号： H01L45/146 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1616

    摘要： ALD processing techniques for forming non-volatile resistive-switching memories are described. In one embodiment, a method includes forming a first electrode on a substrate, maintaining a pedestal temperature for an atomic layer deposition (ALD) process of less than 100° Celsius, forming at least one metal oxide layer over the first electrode, wherein the forming the at least one metal oxide layer is performed using the ALD process using a purge duration of less than 20 seconds, and forming a second electrode over the at least one metal oxide layer.

    摘要翻译： 描述用于形成非易失性电阻式切换存储器的ALD处理技术。 在一个实施例中，一种方法包括在衬底上形成第一电极，保持小于100℃的原子层沉积（ALD）工艺的基座温度，在第一电极上形成至少一个金属氧化物层，其中形成 所述至少一个金属氧化物层使用ALD工艺，使用小于20秒的吹扫持续时间，并在所述至少一个金属氧化物层上形成第二电极。

    Closed-loop sputtering controlled to enhance electrical characteristics in deposited layer
    7.
    发明授权
    Closed-loop sputtering controlled to enhance electrical characteristics in deposited layer 有权
    控制闭环溅射以增强沉积层中的电特性

    公开(公告)号：US08053364B2

    公开(公告)日：2011-11-08

    申请号：US12243322

    申请日：2008-10-01

    申请人： Wayne French ,  Pragati Kumar ,  Prashant Phatak ,  Tony Chiang

    发明人： Wayne French ,  Pragati Kumar ,  Prashant Phatak ,  Tony Chiang

    IPC分类号： H01L21/44 ,  C23C14/00

    CPC分类号： C23C14/083 ,  C23C14/0042 ,  C23C14/54 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/165

    摘要： This disclosure provides a method of fabricating a semiconductor device layer and an associated memory cell. Empirical data may be used to generate a hysteresis curve associated with metal oxide deposition for a metal-insulator-metal structure, with curve measurements reflecting variance of a desired electrical property as a function of cathode voltage used during a sputtering process that uses a biased target. By generating at least one voltage level to be used during the sputtering process, where the voltage reflects a suitable value for the electrical property from among the values obtainable in mixed-mode deposition, a semiconductor device layer may be produced with improved characteristics and durability. A multistable memory cell or array of such cells manufactured according to this process can, for a set of given materials (e.g., metals and oxygen source), be fabricated to have minimal leakage or “off” current characteristics (Ileak or Ioff, respectively) or a maximum ratio of “on” current to “off” current (Ion/Ioff).

    摘要翻译： 本公开提供了制造半导体器件层和相关联的存储单元的方法。 经验数据可用于产生与金属 - 绝缘体 - 金属结构的金属氧化物沉积相关联的滞后曲线，曲线测量反映了在使用偏置目标的溅射过程期间所使用的阴极电压的期望电特性的变化 。 通过在溅射过程中产生要使用的至少一个电压电平，其中电压从混合模式沉积中可获得的值中反映适合的电特性值，可以制造具有改进的特性和耐久性的半导体器件层。 对于一组给定的材料（例如金属和氧源），可以制造这样的电池的多电平存储器单元或阵列，以便具有最小的泄漏或“截止”电流特性（分别为Ileak或Ioff） 或“关”电流与“关”电流（Ion / Ioff）的最大比例。

    TITANIUM-BASED HIGH-K DIELECTRIC FILMS
    8.
    发明申请
    TITANIUM-BASED HIGH-K DIELECTRIC FILMS 有权
    基于钛的高K电介质膜

    公开(公告)号：US20110203085A1

    公开(公告)日：2011-08-25

    申请号：US13100538

    申请日：2011-05-04

    申请人： Hanhong Chen ,  Pragati Kumar ,  Sunil Shanker ,  Edward Haywood ,  Sandra Malhotra ,  Imran Hashim ,  Nobi Fuchigami ,  Prashant Phatak ,  Monica Mathur

    发明人： Hanhong Chen ,  Pragati Kumar ,  Sunil Shanker ,  Edward Haywood ,  Sandra Malhotra ,  Imran Hashim ,  Nobi Fuchigami ,  Prashant Phatak ,  Monica Mathur

    IPC分类号： H01G7/00

    CPC分类号： H01G4/1218 ,  C23C16/405 ,  C23C16/45531 ,  C23C16/56 ,  H01G4/33 ,  H01L21/02186 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/02312 ,  H01L21/02337 ,  H01L21/3141 ,  H01L21/3142 ,  H01L28/40

    摘要： This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on titanium oxide, to suppress the formation of anatase-phase titanium oxide and (b) related devices and structures. A metal-insulator-metal (“MIM”) stack is formed using an ozone pretreatment process of a bottom electrode (or other substrate) followed by an ALD process to form a TiO2 dielectric, rooted in the use of an amide-containing precursor. Following the ALD process, an oxidizing anneal process is applied in a manner is hot enough to heal defects in the TiO2 dielectric and reduce interface states between TiO2 and electrode; the anneal temperature is selected so as to not be so hot as to disrupt BEL surface roughness. Further process variants may include doping the titanium oxide, pedestal heating during the ALD process to 275-300 degrees Celsius, use of platinum or ruthenium for the BEL, and plural reagent pulses of ozone for each ALD process cycle. The process provides high deposition rates, and the resulting MIM structure has substantially no x-ray diffraction peaks associated with anatase-phase titanium oxide.

    摘要翻译： 本公开内容提供（a）制造基于氧化钛的氧化物层（例如电介质层）的方法，以抑制锐钛矿相氧化钛的形成和（b）相关的器件和结构。 使用底部电极（或其他基底）的臭氧预处理随后进行ALD工艺来形成金属 - 绝缘体 - 金属（“MIM”）堆叠，以形成根植于含酰胺前体的TiO 2电介质。 在ALD工艺之后，氧化退火工艺的应用热度足以愈合TiO2电介质中的缺陷，并降低TiO2和电极之间的界面态; 选择退火温度以使其不那么热，以致破坏BEL表面粗糙度。 进一步的工艺变型可以包括在ALD工艺期间掺杂氧化钛，基座加热至275-300摄氏度，对于BEL使用铂或钌，对于每个ALD工艺循环使用多个试剂脉冲的臭氧。 该方法提供高沉积速率，并且所得MIM结构基本上没有与锐钛矿相氧化钛相关的x射线衍射峰。

    CLOSED-LOOP SPUTTERING CONTROLLED TO ENHANCE ELECTRICAL CHARACTERISTICS IN DEPOSITED LAYER
    9.
    发明申请
    CLOSED-LOOP SPUTTERING CONTROLLED TO ENHANCE ELECTRICAL CHARACTERISTICS IN DEPOSITED LAYER 有权
    控制加密环境中的电气特性的隐蔽环

    公开(公告)号：US20090273087A1

    公开(公告)日：2009-11-05

    申请号：US12243322

    申请日：2008-10-01

    申请人： Wayne French ,  Pragati Kumar ,  Prashant Phatak ,  Tony Chiang

    发明人： Wayne French ,  Pragati Kumar ,  Prashant Phatak ,  Tony Chiang

    IPC分类号： H01L23/48 ,  C23C14/34

    CPC分类号： C23C14/083 ,  C23C14/0042 ,  C23C14/54 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/165

    摘要： This disclosure provides a method of fabricating a semiconductor device layer and an associated memory cell. Empirical data may be used to generate a hysteresis curve associated with metal oxide deposition for a metal-insulator-metal structure, with curve measurements reflecting variance of a desired electrical property as a function of cathode voltage used during a sputtering process that uses a biased target. By generating at least one voltage level to be used during the sputtering process, where the voltage reflects a suitable value for the electrical property from among the values obtainable in mixed-mode deposition, a semiconductor device layer may be produced with improved characteristics and durability. A multistable memory cell or array of such cells manufactured according to this process can, for a set of given materials (e.g., metals and oxygen source), be fabricated to have minimal leakage or “off” current characteristics (Ileak or Ioff, respectively) or a maximum ratio of “on” current to “off” current (Ion/Ioff).

    摘要翻译： 本公开提供了制造半导体器件层和相关联的存储单元的方法。 经验数据可用于产生与金属 - 绝缘体 - 金属结构的金属氧化物沉积相关联的滞后曲线，曲线测量反映了在使用偏置目标的溅射过程期间所使用的阴极电压的期望电特性的变化 。 通过在溅射过程中产生要使用的至少一个电压电平，其中电压从混合模式沉积中可获得的值中反映适合的电特性值，可以制造具有改进的特性和耐久性的半导体器件层。 对于一组给定的材料（例如金属和氧源），可以制造这样的电池的多电平存储器单元或阵列，以便具有最小的泄漏或“截止”电流特性（分别为Ileak或Ioff） 或“关”电流与“关”电流（Ion / Ioff）的最大比例。