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    Low Latency Clock Gating Scheme for Power Reduction in Bus Interconnects
    1.
    发明申请
    Low Latency Clock Gating Scheme for Power Reduction in Bus Interconnects 审中-公开
    总线互连功率降低的低延迟时钟门控方案

    公开(公告)号：US20130117593A1

    公开(公告)日：2013-05-09

    申请号：US13290250

    申请日：2011-11-07

    申请人： Prudhvi N. Nooney ,  Jaya Prakash Subramaniam Ganasan ,  Joseph L. Van Swearingen ,  Richard Gerard Hofmann

    发明人： Prudhvi N. Nooney ,  Jaya Prakash Subramaniam Ganasan ,  Joseph L. Van Swearingen ,  Richard Gerard Hofmann

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3237 ,  G06F1/3253 ,  Y02D10/128 ,  Y02D10/151 ,  Y02D50/20

    摘要： A System-on-a-Chip (SoC) comprising a controller, an activity counter, a reference pattern detection logic, a master pattern detection logic, an arbiter, a comparator, a tracker circuit, a delay cell circuit, and a request mask circuit coupled to a bus. The bus is configured to support master control. The controller is configured to cause components to enter a low power state. The activity counter is configured to monitor activity. The detection logics are configured to operate on an activity based clock or always on clock. The arbiter is configured to select an initiator. The comparator is configured to compare the output of the detection logics. The tracker circuit is configured to track selection of components. The delay cell circuit is configured to store output of components. The request mask circuit is configured to prevent request to arbiter or any arbiter selected request made from a previous clock cycle.

    摘要翻译： 一种片上系统（SoC），包括控制器，活动计数器，参考模式检测逻辑，主模式检测逻辑，仲裁器，比较器，跟踪器电路，延迟单元电路和请求掩码 电路耦合到总线。 总线配置为支持主控制。 控制器被配置为使组件进入低功率状态。 活动计数器配置为监视活动。 检测逻辑被配置为在基于活动的时钟上操作或者始终处于时钟上。 仲裁器被配置为选择启动器。 比较器配置为比较检测逻辑的输出。 跟踪器电路被配置为跟踪组件的选择。 延迟单元电路被配置为存储组件的输出。 请求屏蔽电路被配置为防止对仲裁器的请求或从先前时钟周期进行的任何仲裁器选择的请求。