公开(公告)号：US09865798B2

公开(公告)日：2018-01-09

申请号：US14630438

申请日：2015-02-24

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu ,  Junjing Bao ,  Xia Li ,  Seung Hyuk Kang

IPC: H01L21/768 ,  H01L21/31 ,  H01L21/311 ,  H01L21/321 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L23/544 ,  G11C11/16

CPC classification number: H01L43/02 ,  G11C11/16 ,  H01L23/544 ,  H01L43/08 ,  H01L43/12 ,  H01L2223/54426 ,  H01L2223/54453

Abstract: A semiconductor device includes an interconnect layer and a bottom electrode of a resistive memory device. The bottom electrode is coupled to the interconnect layer, and the bottom electrode is comprised of cobalt tungsten phosphorus (CoWP).

公开(公告)号：US09666792B2

公开(公告)日：2017-05-30

申请号：US14824507

申请日：2015-08-12

Applicant: QUALCOMM Incorporated

Inventor： Wei-Chuan Chen ,  Yu Lu ,  Chando Park ,  Seung Hyuk Kang

IPC: H01L21/02 ,  H01L43/12 ,  H01L43/08 ,  H01L27/22 ,  H01L43/02

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08

Abstract: Shadow-effect compensated fabrication of magnetic tunnel junction (MTJ) semiconductor elements is disclosed. Providing shadow-effect compensated fabrication of MTJ elements can provide reduced free layer sizing for enhanced MTJ operational margin. In certain aspects, to reduce size of a free layer during fabrication of an MTJ to provide enhanced write and retention symmetry, ion beam etching (IBE) fabrication process is employed to fabricate a free layer smaller than the pinned layer. To avoid asymmetrical footing being fabricated in free layer due to shadow-effect of neighboring MTJs, an ion beam directed at the MTJ is shadow-effect compensated. The angle of incidence of the ion beam directed at the MTJ is varied as the MTJ is rotated to be less steep when another MTJ is in directional line of the ion beam and the MTJ being fabricated. Thus, the free layer is etched more uniformly in the MTJ while avoiding increased etching damage.

公开(公告)号：US09576801B2

公开(公告)日：2017-02-21

申请号：US14556983

申请日：2014-12-01

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Jeffrey Junhao Xu ,  Zhongze Wang ,  Bin Yang ,  Xiaonan Chen ,  Yu Lu

IPC: H01L27/11 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L29/788 ,  H01L21/02 ,  G11C16/04

CPC classification number: H01L21/28088 ,  G11C16/0408 ,  H01L21/02148 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/28273 ,  H01L21/28291 ,  H01L29/4966 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7851 ,  H01L29/7883

Abstract: Non-volatile memory devices and logic devices are fabricated using processes compatible with high dielectric constant/metal gate (HK/MG) processes for increased cell density and larger scale integration. A doped oxide layer, such as a silicon-doped hafnium oxide (HfO2) layer, is implemented as a ferroelectric dipole layer in a nonvolatile memory device.

Abstract translation: 使用与高介电常数/金属栅（HK / MG）工艺兼容的工艺制造非易失性存储器件和逻辑器件，用于增加电池密度和更大规模的集成。 掺杂氧化物层，例如掺杂硅的氧化铪（HfO 2）层，在非易失性存储器件中被实现为铁电偶极子层。

公开(公告)号：US09548333B2

公开(公告)日：2017-01-17

申请号：US14496525

申请日：2014-09-25

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu ,  Xia Li ,  Seung Hyuk Kang

IPC: H01L27/22 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L45/02 ,  H01L45/00 ,  H01L43/08 ,  H01L43/12

CPC classification number: H01L27/222 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L43/08 ,  H01L43/12 ,  H01L45/02 ,  H01L45/08 ,  H01L45/12 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Systems and methods of integration of resistive memory elements with logic elements in advanced nodes with improved mechanical stability and reduced parasitic capacitance include a resistive memory element and a logic element formed in a common integration layer extending between a bottom cap layer and a top cap layer. At least a first intermetal dielectric (IMD) layer of high-K value is formed in the common integration layer and surrounding at least the resistive memory element, to provide high rigidity and mechanical stability. A second IMD layer of low-K value to reduce parasitic capacitance of the logic element is formed in either the common integration layer, a top layer above the top cap layer or an intermediate layer in between the top and bottom cap layers. Air gaps may be formed in one or more IMD layers to further reduce capacitance.

Abstract translation: 电阻式存储器元件与具有改进的机械稳定性和减小的寄生电容的先进节点中的逻辑元件的集成的系统和方法包括形成在底盖层和顶盖层之间延伸的公共集成层中的电阻存储元件和逻辑元件。 至少在公共积分层中形成高K值的第一金属间电介质（IMD）层，并且至少围绕电阻式存储元件，以提供高刚性和机械稳定性。 降低逻辑元件的寄生电容的低K值的第二IMD层形成在公共集成层，顶盖层上的顶层或顶盖层之间的中间层。 可以在一个或多个IMD层中形成气隙，以进一步降低电容。

公开(公告)号：US20160248002A1

公开(公告)日：2016-08-25

申请号：US14630438

申请日：2015-02-24

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu ,  Junjing Bao ,  Xia Li ,  Seung Hyuk Kang

IPC: H01L43/02 ,  H01L43/12 ,  G11C11/16 ,  H01L43/08

CPC classification number: H01L43/02 ,  G11C11/16 ,  H01L23/544 ,  H01L43/08 ,  H01L43/12 ,  H01L2223/54426 ,  H01L2223/54453

Abstract: A semiconductor device includes an interconnect layer and a bottom electrode of a resistive memory device. The bottom electrode is coupled to the interconnect layer, and the bottom electrode is comprised of cobalt tungsten phosphorus (CoWP).

Abstract translation: 半导体器件包括电阻式存储器件的互连层和底部电极。 底部电极耦合到互连层，底部电极由钴钨磷（CoWP）组成。

公开(公告)号：US09318696B2

公开(公告)日：2016-04-19

申请号：US14195566

申请日：2014-03-03

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu ,  Xia Li ,  Seung Hyuk Kang ,  Shiqun Gu

IPC: H01L21/00 ,  H01L43/12 ,  H01L43/08 ,  H01L43/02 ,  H01L27/22

CPC classification number: H01L43/12 ,  H01L21/76802 ,  H01L21/76813 ,  H01L21/76832 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08

Abstract: Systems and methods for forming precise and self-aligned top metal contact for a Magnetoresistive random-access memory (MRAM) device include forming a magnetic tunnel junction (MTJ) in a common interlayer metal dielectric (IMD) layer with a logic element. A low dielectric constant (K) etch stop layer is selectively retained over an exposed top surface of the MTJ. Etching is selectively performed through a top IMD layer formed over the low K etch stop layer and the common IMD layer, based on a first chemistry which prevents etching through the low K etch stop layer. By switching chemistry to a second chemistry which precisely etches through the low K etch stop layer, an opening is created for forming a self-aligned top contact to the exposed top surface of the MTJ.

Abstract translation: 用于形成用于磁阻随机存取存储器（MRAM）器件的精确和自对准的顶部金属接触的系统和方法包括在具有逻辑元件的公共层间金属电介质（IMD）层中形成磁性隧道结（MTJ）。 低介电常数（K）蚀刻停止层选择性地保留在MTJ的暴露的顶表面上。 基于防止蚀刻通过低K蚀刻停止层的第一化学反应，通过形成在低K蚀刻停止层和公共IMD层上的顶部IMD层选择性地进行蚀刻。 通过将化学转换成精确地蚀刻通过低K蚀刻停止层的第二化学物质，形成一个开口以形成与MTJ暴露的顶表面的自对准顶部接触。

公开(公告)号：US09721634B2

公开(公告)日：2017-08-01

申请号：US14860931

申请日：2015-09-22

Applicant: QUALCOMM Incorporated

Inventor： Xiaochun Zhu ,  Yu Lu ,  Chando Park ,  Seung Hyuk Kang

IPC: G11C11/16 ,  H01L27/22

CPC classification number: G11C11/1659 ,  G11C11/02 ,  G11C11/161 ,  H01L27/228

Abstract: Magnetic tunnel junction (MTJ) memory bit cells that decouple source line layout from access transistor node size to facilitate reduced contact resistance are disclosed. In one example, an MTJ memory bit cell is provided that includes a source plate disposed above and in contact with a source contact for a source node of an access transistor. A source line is disposed above and in electrical contact with the source plate to electrically connect the source line to the source node. The source plate allows the source line to be provided in a higher metal level from the source and drain contacts of the access transistor such that the source line is not in physical contact with (i.e., decoupled from) the source contact. This allows pitch between the source line and drain column to be relaxed from the width of the source and drain nodes without having to increase contact resistance.

公开(公告)号：US20170062526A1

公开(公告)日：2017-03-02

申请号：US14835314

申请日：2015-08-25

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu ,  Xia LI ,  Seung Hyuk KANG

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2463 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1683

Abstract: A method of fabrication of a device includes forming a first electrode and a second electrode. The method further includes forming a resistive material between the first electrode and the second electrode to form a resistance-based storage element of a resistive random access memory (RRAM) device.

Abstract translation: 一种制造器件的方法包括形成第一电极和第二电极。 该方法还包括在第一电极和第二电极之间形成电阻材料以形成电阻随机存取存储器（RRAM）装置的基于电阻的存储元件。

公开(公告)号：US09570509B2

公开(公告)日：2017-02-14

申请号：US14609169

申请日：2015-01-29

Applicant: QUALCOMM Incorporated

Inventor： Vladimir Machkaoutsan ,  Matthias Georg Gottwald ,  Mustafa Badaroglu ,  Jimmy Kan ,  Kangho Lee ,  Yu Lu ,  Chando Park

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/12 ,  H01L43/02

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08

Abstract: A semiconductor device includes a first magnetic tunnel junction (MTJ) device, a second MTJ device, and a top electrode. The first MTJ device includes a barrier layer. The second MTJ device includes the barrier layer. The top electrode is coupled to the first MTJ device and the second MTJ device.

Abstract translation: 半导体器件包括第一磁隧道结（MTJ）器件，第二MTJ器件和顶电极。 第一MTJ装置包括阻挡层。 第二MTJ装置包括阻挡层。 顶部电极耦合到第一MTJ装置和第二MTJ装置。

公开(公告)号：US09548096B1

公开(公告)日：2017-01-17

申请号：US14835871

申请日：2015-08-26

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Yu Lu ,  Xiaochun Zhu

IPC: G11C11/00 ,  G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  H01L27/228

Abstract: Reverse complement MTJ bit cells employing shared source lines are disclosed. In one aspect, a 2T2MTJ reverse complement bit cell employing shared source line is provided. Bit cell includes first MTJ and second MTJ. Value of first MTJ is complement of value of second MTJ. First bit line is coupled to top layer of first MTJ, and first electrode of first access transistor is coupled to bottom layer of first MTJ. Second bit line is coupled to bottom layer of second MTJ, and first electrode of second access transistor is coupled to top layer of second MTJ. Word line is coupled to second electrode of first access transistor and second access transistor. Shared source line is coupled to third electrode of first access transistor and second access transistor. Employing shared source line allows the bit cell to be designed with reduced parasitic resistance.

Abstract translation: 公开了采用共享源线的反向补码MTJ比特单元。 在一个方面，提供了采用共享源线的2T2MTJ反向补码位单元。 位单元包括第一MTJ和第二MTJ。 第一MTJ的价值是第二MTJ的价值的补充。 第一位线耦合到第一MTJ的顶层，第一存取晶体管的第一电极耦合到第一MTJ的底层。 第二位线耦合到第二MTJ的底层，第二存取晶体管的第一电极耦合到第二MTJ的顶层。 字线耦合到第一存取晶体管和第二存取晶体管的第二电极。 共享源极线耦合到第一存取晶体管和第二存取晶体管的第三电极。 采用共享源极线允许位单元被设计成具有减小的寄生电阻。