公开(公告)号：US06602781B1

公开(公告)日：2003-08-05

申请号：US09734207

申请日：2000-12-12

申请人： Qi Xiang ,  Paul R. Besser ,  Matthew Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

发明人： Qi Xiang ,  Paul R. Besser ,  Matthew Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

IPC分类号： H01L2144

CPC分类号： H01L21/28202 ,  H01L21/28097 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7833

摘要： A method for implementing a self-aligned metal silicide gate is achieved by confining a metal within a recess overlying a channel and annealing to cause metal and its overlying silicon to interact to form the self-aligned metal silicide gate. A gate dielectric layer formed of oxynitride or a nitride/oxide stack is formed on the bottom and sidewalls of the recess prior to depositing the silicon. The metal is removed except for the portion of the metal in the recess. A planarization step is performed to remove the remaining unreacted silicon by chemical mechanical polishing until no silicon is detected.

摘要翻译： 实现自对准金属硅化物栅极的方法是通过将金属限制在覆盖沟道的凹槽内并退火以使金属及其上覆的硅相互作用以形成自对准的金属硅化物栅极来实现的。 在沉积硅之前，在凹陷的底部和侧壁上形成由氧氮化物或氮化物/氧化物堆叠形成的栅极电介质层。 除了金属在凹部中的部分之外，除去金属。 进行平面化步骤以通过化学机械抛光除去剩余的未反应的硅，直到没有检测到硅。

公开(公告)号：US06465309B1

公开(公告)日：2002-10-15

申请号：US09734185

申请日：2000-12-12

申请人： Qi Xiang ,  Paul R. Besser ,  Matthew Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

发明人： Qi Xiang ,  Paul R. Besser ,  Matthew Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

IPC分类号： H01L21336

CPC分类号： H01L21/28202 ,  H01L21/28097 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545

摘要： A semiconductor structure and method for making the same provides a gate dielectric formed of oxynitride or a nitride/oxide stack formed within a recess. Amorphous silicon is deposited on the gate dielectric within the recess and a metal is deposited on the amorphous silicon. An annealing process forms a metal silicide gate within the recess on the gate dielectric. A wider range of metal materials can be selected because the gate dielectric formed of oxynitride or a nitride/oxide stack remains stable during the silicidation process. The metal silicide gate significantly reduces the sheet resistance between the gate and gate terminal.

摘要翻译： 半导体结构及其制造方法提供由氧氮化物形成的栅极电介质或形成在凹部内的氮化物/氧化物堆叠。 非晶硅沉积在凹槽内的栅极电介质上，金属沉积在非晶硅上。 退火工艺在栅极电介质的凹槽内形成金属硅化物栅极。 可以选择更宽范围的金属材料，因为由氮氧化物或氮化物/氧化物堆叠形成的栅极电介质在硅化过程中保持稳定。 金属硅化物栅极显着降低了栅极和栅极端子之间的薄层电阻。

公开(公告)号：US06368950B1

公开(公告)日：2002-04-09

申请号：US09734186

申请日：2000-12-12

申请人： Qi Xiang ,  Paul R. Besser ,  Matthew S. Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

发明人： Qi Xiang ,  Paul R. Besser ,  Matthew S. Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

IPC分类号： H01L213205

CPC分类号： H01L29/66545 ,  H01L21/28097

摘要： A method for implementing a self-aligned metal silicide gate is achieved by confining amorphous silicon within a recess overlying a channel and annealing to cause the amorphous silicon with its overlying metal to interact to form the self-aligned metal silicide gate. A gate dielectric layer formed of oxynitride or a nitride/oxide stack is formed on the bottom and sidewalls of the recess prior to depositing the silicon. The silicon is removed except for the portion of the silicon in the recess. The remaining portions of the metal are removed by manipulating the etch selectivity between the metal and the self-aligned metal silicide gate.

摘要翻译： 实现自对准金属硅化物栅极的方法是通过将非晶硅限制在覆盖沟道的凹槽中并退火以使非晶硅与其上覆金属相互作用以形成自对准金属硅化物栅极来实现的。 在沉积硅之前，在凹陷的底部和侧壁上形成由氧氮化物或氮化物/氧化物堆叠形成的栅极电介质层。 除了凹部中硅的部分之外，除去硅。 通过操纵金属和自对准金属硅化物栅之间的蚀刻选择性来去除金属的剩余部分。

公开(公告)号：US06342414B1

公开(公告)日：2002-01-29

申请号：US09734189

申请日：2000-12-12

申请人： Qi Xiang ,  Paul R. Besser ,  Matthew S. Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

发明人： Qi Xiang ,  Paul R. Besser ,  Matthew S. Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

IPC分类号： H01L218238

CPC分类号： H01L21/28194 ,  H01L21/28097 ,  H01L21/28114 ,  H01L29/495 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545

摘要： A method for implementing a self-aligned low temperature metal silicide gate is achieved by confining a low temperature silicidation metal within a recess overlying a channel and annealing to cause the low temperature silicidation metal and its overlying silicon to interact to form the self-aligned low temperature metal silicide gate. A planarization step is performed to remove the remaining unreacted silicon by chemical mechanical polishing until no silicon is detected.

摘要翻译： 实现自对准低温金属硅化物栅极的方法是通过将低温硅化金属限制在覆盖沟道的凹槽内并进行退火以使低温硅化金属及其上覆的硅相互作用以形成自对准低 温度金属硅化物门。 进行平面化步骤以通过化学机械抛光除去剩余的未反应的硅，直到没有检测到硅。

公开(公告)号：US06562718B1

公开(公告)日：2003-05-13

申请号：US09729700

申请日：2000-12-06

申请人： Qi Xiang ,  Ercan Adem ,  Jacques J. Bertrand ,  Paul R. Besser ,  Matthew S. Buynoski ,  John C. Foster ,  Paul L. King ,  George J. Kluth ,  Minh V. Ngo ,  Eric N. Paton ,  Christy Mei-Chu Woo

发明人： Qi Xiang ,  Ercan Adem ,  Jacques J. Bertrand ,  Paul R. Besser ,  Matthew S. Buynoski ,  John C. Foster ,  Paul L. King ,  George J. Kluth ,  Minh V. Ngo ,  Eric N. Paton ,  Christy Mei-Chu Woo

IPC分类号： H01L2144

CPC分类号： H01L29/66507 ,  H01L21/28097

摘要： A method of forming a fully silicidized gate of a semiconductor device includes forming silicide in active regions and a portion of a gate. A shield layer is blanket deposited over the device. The top surface of the gate electrode is then exposed. A refractory metal layer is deposited and annealing is performed to cause the metal to react with the gate and fully silicidize the gate, with the shield layer protecting the active regions of the device from further silicidization to thereby prevent spiking and current leakage in the active regions.

摘要翻译： 形成半导体器件的完全硅化栅极的方法包括在有源区和门的一部分中形成硅化物。 屏蔽层被覆盖在该器件上。 然后露出栅电极的顶表面。 沉积难熔金属层并进行退火以使金属与栅极反应并使栅极完全硅化，屏蔽层保护器件的有源区不受另外的硅化，从而防止有源区中的峰值和电流泄漏 。

公开(公告)号：US06475874B2

公开(公告)日：2002-11-05

申请号：US09731031

申请日：2000-12-07

申请人： Qi Xiang ,  Paul R. Besser ,  Matthew S. Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

发明人： Qi Xiang ,  Paul R. Besser ,  Matthew S. Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

IPC分类号： H01L2120

CPC分类号： H01L21/28194 ,  H01L21/28097 ,  H01L29/495 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545

摘要： A method for implementing a self-aligned low temperature metal silicide gate is achieved by confining amorphous silicon within a recess overlying a channel and annealing to cause the amorphous silicon with its overlying low temperature silicidation metal to interact to form the self-aligned low temperature metal silicide gate. A precursor having a temporary gate is used to form the self-aligned low temperature silicide gate. The remaining portions of the low temperature silicidation metal is removed by manipulating the etch selectivity between the low temperature silicidation metal and the self-aligned low temperature metal silicide gate.

摘要翻译： 实现自对准低温金属硅化物栅极的方法是通过将非晶硅限制在覆盖沟道的凹槽中并退火以使非晶硅与其上覆的低温硅化金属相互作用以形成自对准的低温金属来实现的 硅化物门 使用具有临时栅极的前体形成自对准低温硅化物栅极。 通过操纵低温硅化金属和自对准的低温金属硅化物栅极之间的蚀刻选择性来除去低温硅化金属的剩余部分。

公开(公告)号：US06372644B1

公开(公告)日：2002-04-16

申请号：US09789765

申请日：2001-02-22

申请人： John C. Foster ,  Paul L. King

发明人： John C. Foster ,  Paul L. King

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L29/665 ,  H01L29/7833

摘要： Bridging between nickel silicide layers on a gate electrode and associated source/drain regions along silicon nitride sidewall spacers is prevented by hydrogen passivation of the exposed surfaces of the silicon nitride sidewall spacers. Embodiments include treating the silicon nitride sidewall spacers with a solution of HF and H2O, at a HF:H2O volume ratio of about 100:1 to about 200:1 for up to about 60 seconds at room temperature. Hydrogen passivation reduces the number of silicon dangling bonds, thereby avoiding reaction with subsequently deposited nickel and, hence, avoiding the formation of a bridging film of nickel silicide on the sidewall spacers.

摘要翻译： 通过氮化硅侧壁间隔物的暴露表面的氢钝化来防止在栅电极上的硅化镍层和沿着氮化硅侧壁间隔物的相关源极/漏极区之间的桥接。 实施方案包括用HF和H 2 O的溶液以约100:1至约200:1的HF:H2O体积比在室温下处理氮化硅侧壁间隔物达约60秒。 氢钝化减少硅悬挂键的数量，从而避免与随后沉积的镍的反应，并因此避免在侧壁间隔物上形成硅化镍桥接膜。

公开(公告)号：US06387804B1

公开(公告)日：2002-05-14

申请号：US09664714

申请日：2000-09-19

申请人： John C. Foster

发明人： John C. Foster

IPC分类号： H01L2144

CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L21/3105

摘要： Shorting between a transistor gate electrode and associated source/drain regions due to metal silicide formation on the sidewall spacers is prevented by passivating the sidewall spacer surfaces with a mixture of ozone and water. Embodiments of the invention include spraying the wafer with or immersing the wafer in, a saturated solution of ozone in water.

摘要翻译： 通过用臭氧和水的混合物钝化侧壁间隔物表面来防止由于侧壁间隔物上的金属硅化物形成而在晶体管栅电极和相关源/漏区之间的短路。 本发明的实施例包括将晶片喷洒或浸入晶片的饱和的臭氧溶液中。

公开(公告)号：US4155136A

公开(公告)日：1979-05-22

申请号：US898179

申请日：1978-04-20

申请人： John C. Foster

发明人： John C. Foster

IPC分类号： A43D79/00 ,  G10K11/16 ,  A43D25/00 ,  G10K11/00

CPC分类号： A43D79/00

摘要： Intensity of vibrations emitted by tool and workpiece acted upon is reduced by an enveloping mat of floppy fibres. In a heel attacher, for instance, the mat reduces by 14 or more decibels, and an operator incurs no risk of injury to his hands should they be in the path of the mat when it is moved to or from a heel and shoe being attached.

摘要翻译： 作用于工具和工件发出的振动强度可以通过软盘的包络垫来减少。 例如，在脚跟接合员中，垫子减少了14个或更多的分贝，并且如果操作者在被移动到或从附着的鞋跟和鞋子移动到垫子的路径中时，操作者不会受到伤害的危险 。

公开(公告)号：US06368963B1

公开(公告)日：2002-04-09

申请号：US09660396

申请日：2000-09-12

申请人： John C. Foster

发明人： John C. Foster

IPC分类号： H01L2144

CPC分类号： H01L29/665

摘要： Shorting between a transistor gate electrode and associated source/drain regions due to metal silicide formation on the sidewall spacers is prevented by passivating the sidewall spacer surfaces with a solution of iodine and ethanol. Embodiments of the invention include spraying the wafer with or immersing the wafer in, a solution of iodine in ethanol.

摘要翻译： 通过用碘和乙醇的溶液钝化侧壁间隔物表面来防止由于侧壁间隔物上的金属硅化物形成而在晶体管栅电极和相关源/漏区之间的短路。 本发明的实施方案包括将晶片或晶片浸入碘中在乙醇中的溶液。