公开(公告)号：US06615341B2

公开(公告)日：2003-09-02

申请号：US09876189

申请日：2001-06-05

申请人： Gilbert C. Sih ,  Qiuzhen Zou ,  Inyup Kang ,  Quaeed Motiwala ,  Deepu John ,  Li Zhang ,  Haitao Zhang ,  Way-Shing Lee ,  Charles E. Sakamaki ,  Prashant A. Kantak ,  Sanjay K. Jha ,  Jian Lin

发明人： Gilbert C. Sih ,  Qiuzhen Zou ,  Inyup Kang ,  Quaeed Motiwala ,  Deepu John ,  Li Zhang ,  Haitao Zhang ,  Way-Shing Lee ,  Charles E. Sakamaki ,  Prashant A. Kantak ,  Sanjay K. Jha ,  Jian Lin

IPC分类号： G06F9302

CPC分类号： G06F9/3816 ,  G06F9/30014 ,  G06F9/30098 ,  G06F9/30149 ,  G06F9/30152 ,  G06F9/3885 ,  G06F15/7857

摘要： A digital signal processor (DSP) employs a variable-length instruction set. A portion of the variable-length instructions may be stored in adjacent locations within memory space with the beginning and ending of instructions occurring across memory word boundaries. The instructions may contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation, or operations, to be performed allowing multiple operations during each clock cycle. The DSP includes multiple data buses, and in particular three data buses. The DSP may also use a register bank that has registers accessible by at least two processing units, allowing multiple operations to be performed on a particular set of data by the multiple processing units, without reading and writing the data to and from a memory. an instruction fetch unit that receives instructions of variable length stored in an instruction memory. An instruction memory may advantageously be separate from the three data memories. An instruction decoder decodes the instructions from the instruction memory and generates control signals that cause data to be exchanged between the various registers, data memories, and functional units, allowing multiple operations to be performed during each clock cycle.

公开(公告)号：US06425070B1

公开(公告)日：2002-07-23

申请号：US09044086

申请日：1998-03-18

申请人： Qiuzhen Zou ,  Gilbert C. Sih ,  Inyup Kang ,  Quaeed Motiwala ,  Deepu John ,  Li Zhang ,  Haitao Zhang ,  Way-Shing Lee

发明人： Qiuzhen Zou ,  Gilbert C. Sih ,  Inyup Kang ,  Quaeed Motiwala ,  Deepu John ,  Li Zhang ,  Haitao Zhang ,  Way-Shing Lee

IPC分类号： G06F9302

CPC分类号： G06F9/3816 ,  G06F9/30014 ,  G06F9/30098 ,  G06F9/30149 ,  G06F9/30152 ,  G06F9/3885 ,  G06F15/7857

摘要： The present invention is a novel and improved method and circuit for digital signal processing. One aspect of the invention calls for the use of a variable length instruction set. A portion of the variable length instructions may be stored in adjacent locations within memory space with the beginning and ending of instructions occurring across memory word boundaries. Furthermore, additional aspects of the invention are realized by having instructions contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation, or operations, to be performed allowing multiple operations during each clock cycle. Thus, multiple operations are performed during each clock cycle, reducing the total number of clock cycles necessary to perform a task. The exemplary DSP includes a set of three data buses over which data may be exchanged with a register bank and three data memories. The use of more than two data buses, and especially three data buses, realizes another aspect of the invention, which is significantly reduced bus contention. One embodiment of the invention calls for the data buses to include one wide bus and two narrow buses. The wide bus is coupled to a wide data memory and the two narrow buses are coupled to two narrow data memories. Another aspect of the invention is realized by the use of a register bank that has registers accessible by at least two processing units. This allows multiple operations to be performed on a particular set of data by the multiple processing units, without reading and writing the data to and from a memory. The processing units in the exemplary embodiment of the invention include an arithmetic logic (ALU) and a multiply-accumulate (MAC) unit. When combined with the use of the multiple bus architecture, highly parallel instructions, or both, an additional aspect of the invention is realized where highly pipelined, multi-operation, processing is performed.

摘要翻译： 本发明是用于数字信号处理的新颖且改进的方法和电路。 本发明的一个方面要求使用可变长度指令集。 可变长度指令的一部分可以存储在存储器空间内的相邻位置，同时跨越存储器字边界的指令的开始和结束。 此外，通过使指令包含可变数量的指令片段来实现本发明的附加方面。 每个指令片段导致执行特定操作或操作，允许在每个时钟周期期间进行多个操作。 因此，在每个时钟周期期间执行多个操作，减少执行任务所需的总时钟周期数。 示例性DSP包括一组三个数据总线，数据可以通过该数据总线与寄存器组和三个数据存储器交换。 使用两条以上的数据总线，特别是三条数据总线，实现了本发明的另一方面，这显着减少了总线竞争。 本发明的一个实施例要求数据总线包括一个宽的总线和两个窄的总线。 宽总线耦合到宽数据存储器，并且两个窄总线耦合到两个窄数据存储器。 通过使用具有可由至少两个处理单元访问的寄存器的寄存器组来实现本发明的另一方面。 这允许通过多个处理单元对特定数据集执行多个操作，而不向存储器读取和写入数据。 本发明的示例性实施例中的处理单元包括算术逻辑（ALU）和乘法累加（MAC）单元。 当结合使用多总线架构，高度并行指令或两者时，实现本发明的另一方面，其中执行高度流水线化，多操作的处理。

公开(公告)号：US07873815B2

公开(公告)日：2011-01-18

申请号：US10794300

申请日：2004-03-04

申请人： Gilbert C. Sih ,  De D. Hsu ,  Way-Shing Lee ,  Xufeng Chen

发明人： Gilbert C. Sih ,  De D. Hsu ,  Way-Shing Lee ,  Xufeng Chen

IPC分类号： G06F7/38

CPC分类号： G06F9/30014 ,  G06F9/30032 ,  G06F9/3875 ,  G06F9/3885 ,  G06F9/3893

摘要： DSP architectures having improved performance are described. In an exemplary architecture, a DSP includes two MAC units and two ALUs, where one of the ALUs replaces an adder for one of the two MAC units. This DSP may be configured to operate in a dual-MAC/single-ALU configuration, a single-MAC/dual-ALU configuration, or a dual-MAC/dual-ALU configuration. This flexibility allows the DSP to handle various types of signal processing operations and improves utilization of the available hardware. The DSP architectures further includes pipeline registers that break up critical paths and allow operations at a higher clock speed for greater throughput.

摘要翻译： 描述了具有改进性能的DSP架构。 在示例性架构中，DSP包括两个MAC单元和两个ALU，其中一个ALU替换两个MAC单元之一的加法器。 该DSP可以被配置为以双MAC /单ALU配置，单MAC /双ALU配置或双MAC /双ALU配置来操作。 这种灵活性允许DSP处理各种类型的信号处理操作，并提高可用硬件的利用率。 DSP架构还包括流水线寄存器，其分解关键路径，并允许以更高的时钟速度进行操作以获得更高的吞吐量。

公开(公告)号：US06606700B1

公开(公告)日：2003-08-12

申请号：US09513979

申请日：2000-02-26

申请人： Gilbert C. Sih ,  Hemant Kumar ,  Way-Shing Lee

发明人： Gilbert C. Sih ,  Hemant Kumar ,  Way-Shing Lee

IPC分类号： G06F1582

CPC分类号： G06F9/3877 ,  G06F7/4812 ,  G06F7/5443 ,  G06F9/3001 ,  G06F9/3893 ,  G06F15/7817

摘要： The invention is a digital signal processor architecture that is designed to speed up frequently-used signal processing computations, such as FIR filters, correlations, FFTs, and DFTs. The architecture uses a coupled dual-MAC architecture (MAC1), (MAC2) and attaches a dual-MAC coprocessor (MAC3), (MAC4) onto it in a unique way to achieve a significant increase in processing capability.

摘要翻译： 本发明是一种数字信号处理器架构，其被设计为加速频繁使用的信号处理计算，例如FIR滤波器，相关性，FFT和DFT。 该架构使用耦合的双MAC架构（MAC1）（MAC2），并以独特的方式将双MAC协处理器（MAC3）（MAC4）附加到其上，以实现处理能力的显着增加。

公开(公告)号：US07184463B2

公开(公告)日：2007-02-27

申请号：US10651446

申请日：2003-08-28

申请人： Douglas Neal Rowitch ,  Way-Shing Lee ,  Thunyachate Ekvetchavit

发明人： Douglas Neal Rowitch ,  Way-Shing Lee ,  Thunyachate Ekvetchavit

IPC分类号： H04B1/69 ,  H04B1/707 ,  H04B1/713

CPC分类号： H04B1/70751 ,  H04B1/70752 ,  H04B1/708 ,  H04B1/709 ,  H04B7/0613 ,  H04J13/004

摘要： Demodulator architectures for processing a received signal in a wireless communications system. The demodulator includes a number of correlators coupled to a combiner. Each correlator typically receives and despreads input samples (which are generated from the received signal) with a respective despreading sequence to provide despread samples. Each correlator then decovers the despread samples to provide decovered “half-symbols” and further demodulates the decovered half-symbols with pilot estimates to generate correlated symbols. The decovering is performed with a Walsh symbol having a length (T) that is half the length (2T) of a Walsh symbol used to cover the data symbols in the transmitted signal. The combiner selectively combines correlated symbols from the assigned correlators to provide demodulated symbols. One or more correlators can be assigned to process one or more instances of each transmitted signal. The pilot estimates used within each assigned correlator to demodulate the decovered half-symbols are generated based on the signal instance being processed by that correlator.

摘要翻译： 用于在无线通信系统中处理接收信号的解调器架构。 解调器包括耦合到组合器的多个相关器。 每个相关器通常以相应的解扩序列接收和解扩输入采样（其从接收信号产生），以提供解扩样本。 每个相关器然后解码解扩样本以提供去除的“半符号”，并且用导频估计进一步解调已解除的半符号以产生相关符号。 使用具有用于覆盖发送信号中的数据符号的沃尔什符号的长度（2T）的一半的长度（T）的沃尔什符号执行解复用。 组合器选择性地组合来自所分配的相关器的相关符号以提供解调符号。 可以分配一个或多个相关器来处理每个发射信号的一个或多个实例。 在每个分配的相关器内使用的导频估计是根据该相关器正在处理的信号实例产生的。

公开(公告)号：US06628702B1

公开(公告)日：2003-09-30

申请号：US09594466

申请日：2000-06-14

申请人： Douglas Neal Rowitch ,  Way-Shing Lee ,  Thunyachate Ekvetchavit

发明人： Douglas Neal Rowitch ,  Way-Shing Lee ,  Thunyachate Ekvetchavit

IPC分类号： H04B1500

CPC分类号： H04B1/70751 ,  H04B1/70752 ,  H04B1/708 ,  H04B1/709 ,  H04B7/0613 ,  H04J13/004

摘要： Demodulator architectures for processing a received signal in a wireless communications system. The demodulator includes a number of correlators coupled to a combiner. Each correlator typically receives and despreads input samples (which are generated from the received signal) with a respective despreading sequence to provide despread samples. Each correlator then decovers the despread samples to provide decovered “half-symbols” and further demodulates the decovered half-symbols with pilot estimates to generate correlated symbols. The decovering is performed with a Walsh symbol having a length (T) that is half the length (2T) of a Walsh symbol used to cover the data symbols in the transmitted signal. The combiner selectively combines correlated symbols from the assigned correlators to provide demodulated symbols. One or more correlators can be assigned to process one or more instances of each transmitted signal. The pilot estimates used within each assigned correlator to demodulate the decovered half-symbols are generated based on the signal instance being processed by that correlator.

公开(公告)号：US20110217969A1

公开(公告)日：2011-09-08

申请号：US13039056

申请日：2011-03-02

申请人： Michael K. Spartz ,  Rajiv R. Nambiar ,  Way-Shing Lee ,  Glenn A. Salaman ,  Francis M. Ngai ,  Reza Shahidi

发明人： Michael K. Spartz ,  Rajiv R. Nambiar ,  Way-Shing Lee ,  Glenn A. Salaman ,  Francis M. Ngai ,  Reza Shahidi

IPC分类号： H04W4/00

CPC分类号： H04W36/14 ,  H04W8/26 ,  H04W72/00 ,  H04W76/16 ,  H04W88/06

摘要： A mobile communication device with multiple subscriptions includes a single baseband-radio frequency (BB-RF) resource chain. A first identity module, such as a subscriber identity module (SIM), a second identity module (e.g., a second SIM), and a controller are communicatively coupled to the single BB-RF resource chain. The first identity module is associated with a first subscription, and the second identity module is associated with a second subscription. The controller may be configured to arbitrate access to the single BB-RF resource chain to perform a first activity that corresponds to the first subscription or a second activity that corresponds to the second subscription. For example, the controller may interrupt a data session processed by the single BB-RF resource chain in response to receiving information indicating that a voice call is to be processed by the single BB-RF resource chain.

摘要翻译： 具有多个订阅的移动通信设备包括单个基带射频（BB-RF）资源链。 诸如订户身份模块（SIM），第二身份模块（例如，第二SIM卡）和控制器的第一身份模块通信地耦合到单个BB-RF资源链。 第一身份模块与第一订阅相关联，并且第二身份模块与第二订阅相关联。 控制器可以被配置为仲裁对单个BB-RF资源链的访问以执行对应于第一订阅的第一活动或对应于第二订阅的第二活动。 例如，控制器可以响应于指示语音呼叫将被单个BB-RF资源链处理的接收信息，中断由单个BB-RF资源链处理的数据会话。

公开(公告)号：US20070116101A1

公开(公告)日：2007-05-24

申请号：US11624194

申请日：2007-01-17

申请人： Douglas Rowitch ,  Way-Shing Lee ,  Thunyachate Ekvetchavit

发明人： Douglas Rowitch ,  Way-Shing Lee ,  Thunyachate Ekvetchavit

IPC分类号： H04B1/00

CPC分类号： H04B1/70751 ,  H04B1/70752 ,  H04B1/708 ,  H04B1/709 ,  H04B7/0613 ,  H04J13/004

摘要： Demodulator architectures for processing a received signal in a wireless communications system. The demodulator includes a number of correlators coupled to a combiner. Each correlator typically receives and despreads input samples (which are generated from the received signal) with a respective despreading sequence to provide despread samples. Each correlator then decovers the despread samples to provide decovered “half-symbols” and further demodulates the decovered half-symbols with pilot estimates to generate correlated symbols. The decovering is performed with a Walsh symbol having a length (T) that is half the length (2T) of a Walsh symbol used to cover the data symbols in the transmitted signal. The combiner selectively combines correlated symbols from the assigned correlators to provide demodulated symbols. One or more correlators can be assigned to process one or more instances of each transmitted signal. The pilot estimates used within each assigned correlator to demodulate the decovered half-symbols are generated based on the signal instance being processed by that correlator.

摘要翻译： 用于在无线通信系统中处理接收信号的解调器架构。 解调器包括耦合到组合器的多个相关器。 每个相关器通常以相应的解扩序列接收和解扩输入采样（其从接收信号产生），以提供解扩样本。 每个相关器然后解码解扩样本以提供去除的“半符号”，并且用导频估计进一步解调已解除的半符号以产生相关符号。 使用具有用于覆盖发送信号中的数据符号的沃尔什符号的长度（2T）的一半的长度（T）的沃尔什符号执行解复用。 组合器选择性地组合来自所分配的相关器的相关符号以提供解调符号。 可以分配一个或多个相关器来处理每个发射信号的一个或多个实例。 在每个分配的相关器内使用的导频估计是根据该相关器正在处理的信号实例产生的。

公开(公告)号：US07031269B2

公开(公告)日：2006-04-18

申请号：US10368888

申请日：2003-02-18

申请人： Way-Shing Lee

发明人： Way-Shing Lee

IPC分类号： H04B3/20

CPC分类号： H04M9/082

摘要： An apparatus and method for echo cancellation is presented. The echo canceller comprises an adaptive filter that tracks the impulse response of the echo path and produces an estimate of the echo. Filter adaptation is controlled by a controller based on the rate of the far-end speech signal, the rate of the near-end signal, an acoustic loss measure, and a double talk hangover indicator. The controller may also comprise a step size adaptation unit for determining the adaptation step size of the adaptive filter. In addition, the controller may comprise a noise replacement unit, which controls replacement of the echo residual signal with comfort noise to ensure echo is completely rejected when only the far-end speaker is talking.

公开(公告)号：US07278043B2

公开(公告)日：2007-10-02

申请号：US10093297

申请日：2002-03-06

申请人： Way-Shing Lee

发明人： Way-Shing Lee

IPC分类号： G06F1/00 ,  G06F1/04 ,  G06F1/12 ,  G06F5/06 ,  G06F15/16

CPC分类号： G06F9/4843

摘要： A method for overload detection according to one embodiment of the invention includes a control process and a data process. In response to a timing signal, the control process sets a state of a timing indicator. Upon execution of a time-constrained operation, the data process checks the state of the timing indicator. In other embodiments, subsequent to an overload detection, an auxiliary data process is configured to execute in a mode that consumes fewer processing cycles.

摘要翻译： 根据本发明的一个实施例的用于过载检测的方法包括控制过程和数据处理。 响应于定时信号，控制过程设置定时指示器的状态。 在执行时间约束的操作时，数据处理检查定时指示器的状态。 在其他实施例中，在过载检测之后，辅助数据处理被配置为以消耗更少处理周期的模式执行。