公开(公告)号：US20100210043A1

公开(公告)日：2010-08-19

申请号：US12371724

申请日：2009-02-16

申请人： Qizhi Liu ,  Ping-Chuan Wang ,  Kimball M. Watson ,  Zhijian J. Yang

发明人： Qizhi Liu ,  Ping-Chuan Wang ,  Kimball M. Watson ,  Zhijian J. Yang

IPC分类号： H01L21/66 ,  G06F19/00

CPC分类号： H01L22/34 ,  H01L2924/3011

摘要： A system, method and device for measuring a depth of a Through-Silicon-Via (TSV) in a semiconductor device region on a wafer during in-line semiconductor fabrication, includes a resistance measurement trench structure having length and width dimensions in a substrate, ohmic contacts on a surface of the substrate disposed on opposite sides of the resistance measurement trench structure, and an unfilled TSV structure in semiconductor device region having an unknown depth. A testing circuit makes contact with the ohmic contacts and measures a resistance therebetween, and a processor connected to the testing circuit calculates a depth of the trench structure and the unfilled TSV structure based on the resistance measurement. The resistance measurement trench structure and the unfilled TSV are created simultaneously during fabrication.

摘要翻译： 在线半导体制造期间，用于测量晶片上的半导体器件区域中的硅硅通孔（TSV）的深度的系统，方法和装置包括在衬底中具有长度和宽度尺寸的电阻测量沟槽结构， 设置在电阻测量沟槽结构的相对侧的衬底的表面上的欧姆接触，以及具有未知深度的半导体器件区域中的未填充的TSV结构。 测试电路与欧姆接触件接触并测量它们之间的电阻，连接到测试电路的处理器基于电阻测量来计算沟槽结构的深度和未填充的TSV结构。 在制造期间同时产生电阻测量沟槽结构和未填充TSV。

公开(公告)号：US07904273B2

公开(公告)日：2011-03-08

申请号：US12371724

申请日：2009-02-16

申请人： Qizhi Liu ,  Ping-Chuan Wang ,  Kimball M. Watson ,  Zhijian J. Yang

发明人： Qizhi Liu ,  Ping-Chuan Wang ,  Kimball M. Watson ,  Zhijian J. Yang

IPC分类号： G06F19/00

CPC分类号： H01L22/34 ,  H01L2924/3011

摘要： A system, method and device for measuring a depth of a Through-Silicon-Via (TSV) in a semiconductor device region on a wafer during in-line semiconductor fabrication, includes a resistance measurement trench structure having length and width dimensions in a substrate, ohmic contacts on a surface of the substrate disposed on opposite sides of the resistance measurement trench structure, and an unfilled TSV structure in semiconductor device region having an unknown depth. A testing circuit makes contact with the ohmic contacts and measures a resistance therebetween, and a processor connected to the testing circuit calculates a depth of the trench structure and the unfilled TSV structure based on the resistance measurement. The resistance measurement trench structure and the unfilled TSV are created simultaneously during fabrication.

摘要翻译： 在线半导体制造期间，用于测量晶片上的半导体器件区域中的硅硅通孔（TSV）的深度的系统，方法和装置包括在衬底中具有长度和宽度尺寸的电阻测量沟槽结构， 设置在电阻测量沟槽结构的相对侧的衬底的表面上的欧姆接触，以及具有未知深度的半导体器件区域中的未填充的TSV结构。 测试电路与欧姆接触件接触并测量它们之间的电阻，连接到测试电路的处理器基于电阻测量来计算沟槽结构的深度和未填充的TSV结构。 在制造期间同时产生电阻测量沟槽结构和未填充TSV。

公开(公告)号：US07238565B2

公开(公告)日：2007-07-03

申请号：US10904985

申请日：2004-12-08

申请人： Fernando Guarin ,  J. Edwin Hostetter, Jr. ,  Stewart E. Rauch, III ,  Ping-Chuan Wang ,  Zhijian J. Yang

发明人： Fernando Guarin ,  J. Edwin Hostetter, Jr. ,  Stewart E. Rauch, III ,  Ping-Chuan Wang ,  Zhijian J. Yang

IPC分类号： H01L21/8249

CPC分类号： H01L29/7304 ,  H01L29/7378

摘要： A method for recovery of degradation caused by avalanche hot carriers is provided that includes subjecting an idle bipolar transistor exhibiting avalanche degradation to a thermal anneal step which increases temperature of the transistor thereby recovering the avalanche degradation of the bipolar transistor. In one embodiment, the annealing source is a self-heating structure that is a Si-containing resistor that is located side by side with an emitter of the bipolar transistor. During the recovering step, the bipolar transistor including the self-heating structure is placed in the idle mode (i.e., without bias) and a current from a separate circuit is flown through the self-heating structure. In another embodiment of the present, the annealing step is a result of providing a high forward current (around the peak fT current or greater) to the bipolar transistor while operating below the avalanche condition (V″CB of less than 1 V). Under the above conditions, about 40% or greater of the degradation can be recovered. In yet another embodiment of the present invention, the thermal annealing step may include a rapid thermal anneal (RTA), a furnace anneal, a laser anneal or a spike anneal.

摘要翻译： 提供了一种用于回收由雪崩热载体引起的降解的方法，其包括使表现出雪崩降解的空闲双极晶体管经历热退火步骤，所述热退火步骤增加了晶体管的温度，从而恢复了双极晶体管的雪崩劣化。 在一个实施例中，退火源是自发热结构，其是与双极晶体管的发射极并排放置的含Si电阻器。 在恢复步骤期间，包括自发热结构的双极晶体管被置于空闲模式（即，没有偏压），并且来自单独电路的电流流过自热结构。 在本发明的另一个实施例中，退火步骤是在低于雪崩状况（V“CB”）的情况下向双极晶体管提供高正向电流（围绕峰值fT电流或更大）的结果， 小于1V）。 在上述条件下，可以回收约40％以上的降解。 在本发明的又一实施例中，热退火步骤可以包括快速热退火（RTA），炉退火，激光退火或尖峰退火。

公开(公告)号：US08193575B2

公开(公告)日：2012-06-05

申请号：US12027496

申请日：2008-02-07

申请人： Louis C. Hsu ,  Xu Ouyang ,  Ping-Chuan Wang ,  Zhijian J. Yang

发明人： Louis C. Hsu ,  Xu Ouyang ,  Ping-Chuan Wang ,  Zhijian J. Yang

IPC分类号： H01L29/788

CPC分类号： H01L21/28273 ,  H01L27/11521 ,  H01L29/7881

摘要： A flash memory structure having an enhanced capacitive coupling coefficient ratio (CCCR) may be fabricated in a self-aligned manner while using a semiconductor substrate that has an active region that is recessed within an aperture with respect to an isolation region that surrounds the active region. The flash memory structure includes a floating gate that does not rise above the isolation region, and that preferably consists of a single layer that has a U shape. The U shape facilitates the enhanced capacitive coupling coefficient ratio.

摘要翻译： 具有增强的电容耦合系数比（CCCR）的闪速存储器结构可以以自对准方式制造，同时使用半导体衬底，该半导体衬底具有相对于围绕有源区域的隔离区域在孔内凹入的有源区域 。 闪速存储器结构包括不在隔离区上方升起的浮栅，并且优选地由具有U形的单层组成。 U形有助于增强电容耦合系数比。

公开(公告)号：US07723824B2

公开(公告)日：2010-05-25

申请号：US11744621

申请日：2007-05-04

申请人： Fernando Guarin ,  J. Edwin Hostetter, Jr. ,  Stewart E. Rauch, III ,  Ping-Chuan Wang ,  Zhijian J. Yang

发明人： Fernando Guarin ,  J. Edwin Hostetter, Jr. ,  Stewart E. Rauch, III ,  Ping-Chuan Wang ,  Zhijian J. Yang

IPC分类号： H01L29/73

CPC分类号： H01L29/7304 ,  H01L29/7378

摘要： A method for recovery of degradation caused by avalanche hot carriers is provided that includes subjecting an idle bipolar transistor exhibiting avalanche degradation to a thermal anneal step which increases temperature of the transistor thereby recovering the avalanche degradation of the bipolar transistor. In one embodiment, the annealing source is a self-heating structure that is a Si-containing resistor that is located side by side with an emitter of the bipolar transistor. During the recovering step, the bipolar transistor including the self-heating structure is placed in the idle mode (i.e., without bias) and a current from a separate circuit is flown through the self-heating structure. In another embodiment of the present, the annealing step is a result of providing a high forward current (around the peak fT current or greater) to the bipolar transistor while operating below the avalanche condition (VCB of less than 1 V). Under the above conditions, about 40% or greater of the degradation can be recovered. In yet another embodiment of the present invention, the thermal annealing step may include a rapid thermal anneal (RTA), a furnace anneal, a laser anneal or a spike anneal.

摘要翻译： 提供了一种用于回收由雪崩热载体引起的降解的方法，其包括使表现出雪崩降解的空闲双极晶体管经历热退火步骤，所述热退火步骤增加了晶体管的温度，从而恢复了双极晶体管的雪崩劣化。 在一个实施例中，退火源是自发热结构，其是与双极晶体管的发射极并排放置的含Si电阻器。 在恢复步骤期间，包括自发热结构的双极晶体管被置于空闲模式（即，没有偏压），并且来自单独电路的电流流过自热结构。 在本发明的另一个实施例中，退火步骤是在低于雪崩条件（VCB小于1V）的情况下向双极晶体管提供高正向电流（围绕峰值fT电流或更大）的结果。 在上述条件下，可以回收约40％以上的降解。 在本发明的又一实施例中，热退火步骤可以包括快速热退火（RTA），炉退火，激光退火或尖峰退火。

公开(公告)号：US20090200598A1

公开(公告)日：2009-08-13

申请号：US12027496

申请日：2008-02-07

申请人： Louis C. Hsu ,  Xu Ouyang ,  Ping-Chuan Wang ,  Zhijian J. Yang

发明人： Louis C. Hsu ,  Xu Ouyang ,  Ping-Chuan Wang ,  Zhijian J. Yang

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L21/28273 ,  H01L27/11521 ,  H01L29/7881

摘要： A flash memory structure having an enhanced capacitive coupling coefficient ratio (CCCR) may be fabricated in a self-aligned manner while using a semiconductor substrate that has an active region that is recessed within an aperture with respect to an isolation region that surrounds the active region. The flash memory structure includes a floating gate that does not rise above the isolation region, and that preferably consists of a single layer that has a U shape. The U shape facilitates the enhanced capacitive coupling coefficient ratio.

摘要翻译： 具有增强的电容耦合系数比（CCCR）的闪速存储器结构可以以自对准方式制造，同时使用半导体衬底，该半导体衬底具有相对于围绕有源区域的隔离区域在孔内凹入的有源区域 。 闪速存储器结构包括不在隔离区上方升起的浮栅，并且优选地由具有U形的单层组成。 U形有助于增强电容耦合系数比。

公开(公告)号：US08422322B2

公开(公告)日：2013-04-16

申请号：US13288472

申请日：2011-11-03

申请人： Louis L. C. Hsu ,  Rajiv V. Joshi ,  Zhijian J. Yang ,  Ping-Chuan Wang

发明人： Louis L. C. Hsu ,  Rajiv V. Joshi ,  Zhijian J. Yang ,  Ping-Chuan Wang

IPC分类号： G11C7/00

CPC分类号： G11C29/04 ,  G11C7/12 ,  G11C11/412

摘要： A method for repairing degraded field effect transistors includes forward biasing PN junctions of one of a source and a drain of a field effect transistor (FET), and a body of the FET. Charge is injected from a substrate to a gate region to neutralize charge in the gate region. The method is applicable to CMOS devices. Repair circuits are disclosed for implementing the repairs.

摘要翻译： 用于修复劣化场效应晶体管的方法包括场效应晶体管（FET）的源极和漏极之一的正偏置PN结以及FET的主体。 电荷从衬底注入到栅极区域以中和栅极区域中的电荷。 该方法适用于CMOS器件。 公开了用于实施修理的维修电路。

公开(公告)号：US08098536B2

公开(公告)日：2012-01-17

申请号：US12019240

申请日：2008-01-24

申请人： Louis L. C. Hsu ,  Rajiv V. Joshi ,  Zhijian J. Yang ,  Ping-Chuan Wang

发明人： Louis L. C. Hsu ,  Rajiv V. Joshi ,  Zhijian J. Yang ,  Ping-Chuan Wang

IPC分类号： G11C7/00

CPC分类号： G11C29/04 ,  G11C7/12 ,  G11C11/412

摘要： A method for repairing degraded field effect transistors includes forward biasing PN junctions of one of a source and a drain of a field effect transistor (FET), and a body of the FET. Charge is injected from a substrate to a gate region to neutralize charge in the gate region. The method is applicable to CMOS devices. Repair circuits are disclosed for implementing the repairs.

摘要翻译： 用于修复劣化场效应晶体管的方法包括场效应晶体管（FET）的源极和漏极之一的正偏置PN结以及FET的主体。 电荷从衬底注入到栅极区域以中和栅极区域中的电荷。 该方法适用于CMOS器件。 公开了用于实施修理的维修电路。

公开(公告)号：US07675378B2

公开(公告)日：2010-03-09

申请号：US12114029

申请日：2008-05-02

申请人： Kai D. Feng ,  Kafai Lai ,  Ping-Chuan Wang ,  Zhijian J. Yang

发明人： Kai D. Feng ,  Kafai Lai ,  Ping-Chuan Wang ,  Zhijian J. Yang

IPC分类号： H03B5/12 ,  H03L7/099

CPC分类号： H03B5/1206 ,  H03B5/1243

摘要： Disclosed are embodiments of a voltage controlled oscillator (VCO) capable of non-volatile self-correction to compensate for process variations and to ensure that the center frequency of the oscillator is maintained within a predetermined frequency range. This VCO incorporates a pair of varactors connected in parallel to an inductor-capacitor (LC) tank circuit for outputting a periodic signal having a frequency that is proportional to an input voltage. A control loop uses a programmable variable resistance e-fuse to set a compensation voltage to be applied to the pair of varactors. By adjusting the compensation voltage, the capacitance of the pair of varactors can be adjusted in order to selectively increase or decrease the frequency of the periodic signal in response to a set input voltage and, thereby to bring the frequency of that periodic signal into the predetermined frequency range. Also disclosed are embodiments of an associated design structure for such a VCO and an associated method for operating such a VCO.

摘要翻译： 公开了能够进行非易失性自校正以补偿过程变化并确保振荡器的中心频率保持在预定频率范围内的压控振荡器（VCO）的实施例。 该VCO包含一对与电感 - 电容（LC）电路并联连接的变容二极管，用于输出具有与输入电压成比例的频率的周期性信号。 控制回路使用可编程可变电阻电熔丝设置要施加到该变容二极管的补偿电压。 通过调整补偿电压，可以调整一对变容二极管的电容，以便响应于设定的输入电压选择性地增加或减小周期信号的频率，从而使该周期信号的频率达到预定的 频率范围。 还公开了用于这种VCO的相关设计结构的实施例以及用于操作这样的VCO的相关方法。

公开(公告)号：US07609121B2

公开(公告)日：2009-10-27

申请号：US12057494

申请日：2008-03-28

申请人： Kai D. Feng ,  Kafai Lai ,  Ping-Chuan Wang ,  Zhijian J. Yang

发明人： Kai D. Feng ,  Kafai Lai ,  Ping-Chuan Wang ,  Zhijian J. Yang

IPC分类号： H03B5/12 ,  H03L7/099

CPC分类号： H03B5/1206 ,  H03B5/1243

摘要： Disclosed are embodiments of a voltage controlled oscillator (VCO) capable of non-volatile self-correction to compensate for process variations and to ensure that the center frequency of the oscillator is maintained within a predetermined frequency range. This VCO incorporates a pair of varactors connected in parallel to an inductor-capacitor (LC) tank circuit for outputting a periodic signal having a frequency that is proportional to an input voltage. A control loop uses a programmable variable resistance e-fuse to set a compensation voltage to be applied to the pair of varactors. By adjusting the compensation voltage, the capacitance of the pair of varactors can be adjusted in order to selectively increase or decrease the frequency of the periodic signal in response to a set input voltage and, thereby to bring the frequency of that periodic signal into the predetermined frequency range. Also disclosed are embodiments of an associated design structure for such a VCO and an associated method for operating such a VCO.

摘要翻译： 公开了能够进行非易失性自校正以补偿过程变化并确保振荡器的中心频率保持在预定频率范围内的压控振荡器（VCO）的实施例。 该VCO包含一对与电感 - 电容（LC）电路并联连接的变容二极管，用于输出具有与输入电压成比例的频率的周期性信号。 控制回路使用可编程可变电阻电熔丝设置要施加到该变容二极管的补偿电压。 通过调整补偿电压，可以调整一对变容二极管的电容，以便响应于设定的输入电压选择性地增加或减小周期信号的频率，从而使该周期信号的频率达到预定的 频率范围。 还公开了用于这种VCO的相关设计结构的实施例以及用于操作这样的VCO的相关方法。