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    Semiconductor integrated circuit device
    2.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US08686885B2

    公开(公告)日：2014-04-01

    申请号：US13744284

    申请日：2013-01-17

    Applicant: Renesas Electronics Corporation

    Inventor： Tatsuji Matsuura ,  Hideo Nakane ,  Masumi Kasahara ,  Ryuichi Ujiie ,  Keisuke Kimura ,  Oshima Takashi

    IPC: H03M1/10

    CPC classification number: H03M1/06 ,  H03M1/1038 ,  H03M1/1071 ,  H03M1/123

    Abstract: A semiconductor integrated circuit device having A/D converters for converting, by means of digital correction processing, analog input signals into digital signals is reduced in area. The semiconductor integrated circuit device has a first A/D converter and a second A/D converter. In a first mode, a first test signal is inputted to both the first and second A/D converters, and a first correction coefficient for the first A/D converter and a second correction coefficient for the second A/D converter are calculated. In a second mode, the first A/D converter converts a first analog signal into a first digital signal by subjecting the first analog signal to a first digital correction processing and the second A/D converter converts a second analog signal into a second digital signal by subjecting the second analog signal to a second digital correction processing.

    Abstract translation: 具有用于通过数字校正处理将模拟输入信号转换成数字信号的A / D转换器的半导体集成电路器件面积减小。 半导体集成电路器件具有第一A / D转换器和第二A / D转换器。 在第一模式中，第一测试信号被输入到第一和第二A / D转换器，并且计算第一A / D转换器的第一校正系数和第二A / D转换器的第二校正系数。 在第二模式中，第一A / D转换器通过对第一模拟信号进行第一数字校正处理而将第一模拟信号转换为第一数字信号，并且第二A / D转换器将第二模拟信号转换为第二数字信号 通过对第二模拟信号进行第二数字校正处理。

    A/D converter circuit and semiconductor integrated circuit
    3.
    发明授权
    A/D converter circuit and semiconductor integrated circuit 有权

    公开(公告)号：US10020814B2

    公开(公告)日：2018-07-10

    申请号：US15594753

    申请日：2017-05-15

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Keisuke Kimura ,  Yuichi Okuda ,  Hideo Nakane ,  Takaya Yamamoto

    IPC: H03M1/06 ,  H03M1/10 ,  H03M1/12 ,  H03M1/00

    CPC classification number: H03M1/0634 ,  H03M1/002 ,  H03M1/0617 ,  H03M1/1009 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/1225

    Abstract: An analog-to-digital converter circuit having a simple design and capable of preventing an increase in surface area and other problems. An analog-to-digital converter circuit for converting an analog input signal to a digital quantity includes an analog-to-digital converter unit that converts analog input signals to pre-correction digital values, and a corrector unit that digitally corrects the pre-connection digital values output from the analog-to-digital converter unit. The corrector unit includes a weighting coefficient multiplier unit that outputs a post-correction digital value obtained by multiplying the weighting coefficients provided for each bit by each bit of the pre-correction digital value output from the A/D converter unit and summing them, and a weighting coefficient search unit that searches for weighting coefficients so as to minimize an error signal generated based on the post-correction digital value and an approximate value for the post-correction digital value.

    A/D converter circuit and semiconductor integrated circuit
    4.
    发明授权
    A/D converter circuit and semiconductor integrated circuit 有权

    公开(公告)号：US09685968B2

    公开(公告)日：2017-06-20

    申请号：US15142273

    申请日：2016-04-29

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Keisuke Kimura ,  Yuichi Okuda ,  Hideo Nakane ,  Takaya Yamamoto

    IPC: H03M1/06 ,  H03M1/10 ,  H03M1/00 ,  H03M1/12

    CPC classification number: H03M1/0634 ,  H03M1/002 ,  H03M1/0617 ,  H03M1/1009 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/1225

    Abstract: An analog-to-digital converter circuit having a simple design and capable of preventing an increase in surface area and other problems. An analog-to-digital converter circuit for converting an analog input signal to a digital quantity includes an analog-to-digital converter unit that converts analog input signals to pre-correction digital values, and a corrector unit that digitally corrects the pre-connection digital values output from the analog-to-digital converter unit. The corrector unit includes a weighting coefficient multiplier unit that outputs a post-correction digital value obtained by multiplying the weighting coefficients provided for each bit by each bit of the pre-correction digital value output from the A/D converter unit and summing them, and a weighting coefficient search unit that searches for weighting coefficients so as to minimize an error signal generated based on the post-correction digital value and an approximate value for the post-correction digital value.

    Semiconductor Device Having Analog-To-Digital Converter With Gain-Dependent Dithering And Communication Apparatus
    6.
    发明申请
    Semiconductor Device Having Analog-To-Digital Converter With Gain-Dependent Dithering And Communication Apparatus 有权
    具有增益依赖抖动和通信设备的模数转换器的半导体器件

    公开(公告)号：US20140333461A1

    公开(公告)日：2014-11-13

    申请号：US14445682

    申请日：2014-07-29

    Applicant: Renesas Electronics Corporation

    Inventor： Keisuke Kimura ,  Yuichi Okuda ,  Hideo Nakane ,  Takaya Yamamoto ,  Tatsuji Matsuura

    IPC: H03M3/00 ,  H03M1/20

    CPC classification number: H03M3/49 ,  H03M1/201 ,  H03M3/328 ,  H03M3/332 ,  H03M3/43 ,  H03M3/438 ,  H03M3/486

    Abstract: A semiconductor communication device reduces influence of noise that is produced by applying a dither signal. The semiconductor communication device includes a Delta-Sigma analog-to-digital converter that converts input analog signals to digital signals, a power detecting unit that detects signal power of the digital signals, a gain control unit that changes a gain setting of analog signals to be input to the Delta-Sigma analog-to-digital converter depending on the signal power of the digital signals, and a dither signal control unit that causes the Delta-Sigma analog-to-digital converter to selectively add the dither signal when the gain setting changes.

    Abstract translation: 半导体通信设备减少通过应用抖动信号产生的噪声的影响。 该半导体通信装置包括将输入的模拟信号转换为数字信号的Delta-Sigma模数转换器，检测数字信号的信号功率的功率检测单元，将模拟信号的增益设定变更为 根据数字信号的信号功率输入到Delta-Sigma模数转换器;以及抖动信号控制单元，其使Delta-Sigma模数转换器在增益时选择性地添加抖动信号 设置更改。

    Semiconductor device and failure detection method
    7.
    发明授权
    Semiconductor device and failure detection method 有权

    公开(公告)号：US10310049B2

    公开(公告)日：2019-06-04

    申请号：US15218006

    申请日：2016-07-23

    Applicant: Renesas Electronics Corporation

    Inventor： Yuichi Okuda ,  Hideo Nakane ,  Takaya Yamamoto ,  Keisuke Kimura ,  Takashi Oshima

    IPC: G01R31/3163 ,  H03M1/10 ,  G01R19/25 ,  G01R35/00 ,  H03M1/46

    Abstract: The present invention provides a semiconductor device and a failure detection method capable of detecting an excessive variation among elements that constitute an analog circuit as a failure. According to an embodiment, a semiconductor device 1 includes: an AD converter 11; a digital assist circuit 12 that corrects an error of a digital signal Do corresponding to an analog signal Ain processed by the AD converter 11; and a failure detection circuit 13 that detects whether the AD converter 11 has a failure based on a correction amount by the digital assist circuit. The semiconductor device 1 is therefore able to detect the excessive variation among the elements that constitute the AD converter 11 as a failure.

    Semiconductor device
    9.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09362931B2

    公开(公告)日：2016-06-07

    申请号：US14750242

    申请日：2015-06-25

    Applicant: Renesas Electronics Corporation

    Inventor： Takaya Yamamoto ,  Hideo Nakane ,  Keisuke Kimura ,  Yuichi Okuda ,  Takashi Oshima

    IPC: H03M1/12 ,  H03M1/00 ,  H03M1/06 ,  H03M1/46 ,  H03M1/10

    CPC classification number: H03M1/002 ,  H03M1/0609 ,  H03M1/0639 ,  H03M1/1009 ,  H03M1/1038 ,  H03M1/124 ,  H03M1/145 ,  H03M1/38 ,  H03M1/462 ,  H03M1/468

    Abstract: There is provided a semiconductor device using low electric power and a small area which can realize highly accurate calibration. The semiconductor device according to the embodiment includes an A/D conversion unit, and a hold signal generating circuit which is coupled to an input side of the A/D conversion unit, and has a hold period not less than two cycles of the A/D conversion unit. The hold signal generating circuit includes: an SC integrator including an input buffer coupled to the input side of the A/D conversion unit, and feedback capacitor coupled to an input and an output of the input buffer; and a logic circuit which compares an output signal of plural bits outputted from the A/D conversion unit with a first and a second threshold values, and outputs a control signal which controls polarity of the SC integrator according to a comparison result.

    Abstract translation: 提供了一种使用低功率和小面积的半导体器件，可以实现高精度的校准。 根据实施例的半导体器件包括A / D转换单元和耦合到A / D转换单元的输入侧的保持信号产生电路，并且具有不少于A / D转换单元的两个周期的保持周期， D转换单元。 保持信号生成电路包括：SC积分器，包括耦合到A / D转换单元的输入侧的输入缓冲器，以及耦合到输入缓冲器的输入和输出的反馈电容器; 以及将从A / D转换单元输出的多个比特的输出信号与第一和第二阈值进行比较的逻辑电路，并根据比较结果输出控制SC积分器的极性的控制信号。

    Semiconductor device having Analog-to-Digital Converter with gain-dependent dithering and communication apparatus
    10.
    发明授权
    Semiconductor device having Analog-to-Digital Converter with gain-dependent dithering and communication apparatus 有权
    具有与增益相关的抖动和通信装置的模数转换器的半导体器件

    公开(公告)号：US09007245B2

    公开(公告)日：2015-04-14

    申请号：US14445682

    申请日：2014-07-29

    Applicant: Renesas Electronics Corporation

    Inventor： Keisuke Kimura ,  Yuichi Okuda ,  Hideo Nakane ,  Takaya Yamamoto ,  Tatsuji Matsuura

    IPC: H03M1/20 ,  H03M3/00

    CPC classification number: H03M3/49 ,  H03M1/201 ,  H03M3/328 ,  H03M3/332 ,  H03M3/43 ,  H03M3/438 ,  H03M3/486

    Abstract: A semiconductor communication device reduces influence of noise that is produced by applying a dither signal. The semiconductor communication device includes a Delta-Sigma analog-to-digital converter that converts input analog signals to digital signals, a power detecting unit that detects signal power of the digital signals, a gain control unit that changes a gain setting of analog signals to be input to the Delta-Sigma analog-to-digital converter depending on the signal power of the digital signals, and a dither signal control unit that causes the Delta-Sigma analog-to-digital converter to selectively add the dither signal when the gain setting changes.

    Abstract translation: 半导体通信设备减少通过应用抖动信号产生的噪声的影响。 该半导体通信装置包括将输入的模拟信号转换为数字信号的Delta-Sigma模数转换器，检测数字信号的信号功率的功率检测单元，将模拟信号的增益设定变更为 根据数字信号的信号功率输入到Delta-Sigma模数转换器;以及抖动信号控制单元，其使Delta-Sigma模数转换器在增益时选择性地添加抖动信号 设置更改。

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