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    Semiconductor device and failure detection method
    3.
    发明授权
    Semiconductor device and failure detection method 有权

    公开(公告)号：US10310049B2

    公开(公告)日：2019-06-04

    申请号：US15218006

    申请日：2016-07-23

    申请人： Renesas Electronics Corporation

    发明人： Yuichi Okuda ,  Hideo Nakane ,  Takaya Yamamoto ,  Keisuke Kimura ,  Takashi Oshima

    IPC分类号： G01R31/3163 ,  H03M1/10 ,  G01R19/25 ,  G01R35/00 ,  H03M1/46

    摘要： The present invention provides a semiconductor device and a failure detection method capable of detecting an excessive variation among elements that constitute an analog circuit as a failure. According to an embodiment, a semiconductor device 1 includes: an AD converter 11; a digital assist circuit 12 that corrects an error of a digital signal Do corresponding to an analog signal Ain processed by the AD converter 11; and a failure detection circuit 13 that detects whether the AD converter 11 has a failure based on a correction amount by the digital assist circuit. The semiconductor device 1 is therefore able to detect the excessive variation among the elements that constitute the AD converter 11 as a failure.

    Semiconductor device
    5.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09362931B2

    公开(公告)日：2016-06-07

    申请号：US14750242

    申请日：2015-06-25

    申请人： Renesas Electronics Corporation

    发明人： Takaya Yamamoto ,  Hideo Nakane ,  Keisuke Kimura ,  Yuichi Okuda ,  Takashi Oshima

    IPC分类号： H03M1/12 ,  H03M1/00 ,  H03M1/06 ,  H03M1/46 ,  H03M1/10

    CPC分类号： H03M1/002 ,  H03M1/0609 ,  H03M1/0639 ,  H03M1/1009 ,  H03M1/1038 ,  H03M1/124 ,  H03M1/145 ,  H03M1/38 ,  H03M1/462 ,  H03M1/468

    摘要： There is provided a semiconductor device using low electric power and a small area which can realize highly accurate calibration. The semiconductor device according to the embodiment includes an A/D conversion unit, and a hold signal generating circuit which is coupled to an input side of the A/D conversion unit, and has a hold period not less than two cycles of the A/D conversion unit. The hold signal generating circuit includes: an SC integrator including an input buffer coupled to the input side of the A/D conversion unit, and feedback capacitor coupled to an input and an output of the input buffer; and a logic circuit which compares an output signal of plural bits outputted from the A/D conversion unit with a first and a second threshold values, and outputs a control signal which controls polarity of the SC integrator according to a comparison result.

    摘要翻译： 提供了一种使用低功率和小面积的半导体器件，可以实现高精度的校准。 根据实施例的半导体器件包括A / D转换单元和耦合到A / D转换单元的输入侧的保持信号产生电路，并且具有不少于A / D转换单元的两个周期的保持周期， D转换单元。 保持信号生成电路包括：SC积分器，包括耦合到A / D转换单元的输入侧的输入缓冲器，以及耦合到输入缓冲器的输入和输出的反馈电容器; 以及将从A / D转换单元输出的多个比特的输出信号与第一和第二阈值进行比较的逻辑电路，并根据比较结果输出控制SC积分器的极性的控制信号。

    Semiconductor device having Analog-to-Digital Converter with gain-dependent dithering and communication apparatus
    6.
    发明授权
    Semiconductor device having Analog-to-Digital Converter with gain-dependent dithering and communication apparatus 有权
    具有与增益相关的抖动和通信装置的模数转换器的半导体器件

    公开(公告)号：US09007245B2

    公开(公告)日：2015-04-14

    申请号：US14445682

    申请日：2014-07-29

    申请人： Renesas Electronics Corporation

    发明人： Keisuke Kimura ,  Yuichi Okuda ,  Hideo Nakane ,  Takaya Yamamoto ,  Tatsuji Matsuura

    IPC分类号： H03M1/20 ,  H03M3/00

    CPC分类号： H03M3/49 ,  H03M1/201 ,  H03M3/328 ,  H03M3/332 ,  H03M3/43 ,  H03M3/438 ,  H03M3/486

    摘要： A semiconductor communication device reduces influence of noise that is produced by applying a dither signal. The semiconductor communication device includes a Delta-Sigma analog-to-digital converter that converts input analog signals to digital signals, a power detecting unit that detects signal power of the digital signals, a gain control unit that changes a gain setting of analog signals to be input to the Delta-Sigma analog-to-digital converter depending on the signal power of the digital signals, and a dither signal control unit that causes the Delta-Sigma analog-to-digital converter to selectively add the dither signal when the gain setting changes.

    摘要翻译： 半导体通信设备减少通过应用抖动信号产生的噪声的影响。 该半导体通信装置包括将输入的模拟信号转换为数字信号的Delta-Sigma模数转换器，检测数字信号的信号功率的功率检测单元，将模拟信号的增益设定变更为 根据数字信号的信号功率输入到Delta-Sigma模数转换器;以及抖动信号控制单元，其使Delta-Sigma模数转换器在增益时选择性地添加抖动信号 设置更改。

    Current generation circuit, and bandgap reference circuit and semiconductor device including the same
    7.
    发明授权
    Current generation circuit, and bandgap reference circuit and semiconductor device including the same 有权

    公开(公告)号：US09891650B2

    公开(公告)日：2018-02-13

    申请号：US15597282

    申请日：2017-05-17

    申请人： Renesas Electronics Corporation

    发明人： Atsushi Motozawa ,  Yuichi Okuda

    IPC分类号： G05F3/30 ,  G05F3/26 ,  G05F3/24

    CPC分类号： G05F3/30 ,  G05F3/245 ,  G05F3/267

    摘要： A current generation circuit including a first and a second bipolar transistors, a current distribution circuit that makes a first current and a second current flow through the first and second bipolar transistors, respectively, the first current and the second current corresponding to a first control voltage, a first NMOS transistor disposed between the first bipolar transistor and the first current distribution circuit, a second NMOS transistor disposed between the second bipolar transistor and the first current distribution circuit, a first resistive element, a first operational amplifier that outputs the second control voltage to the gates of the first and the second NMOS transistors according to a drain voltage of the first NMOS transistor and a reference bias voltage, and a second operational amplifier that generates the first control voltage according to a drain voltage of the second NMOS transistor and the reference bias voltage.

    CRYSTAL OSCILLATION DEVICE AND SEMICONDUCTOR DEVICE
    10.
    发明申请
    CRYSTAL OSCILLATION DEVICE AND SEMICONDUCTOR DEVICE 有权
    晶体振荡器件和半导体器件

    公开(公告)号：US20160164461A1

    公开(公告)日：2016-06-09

    申请号：US15043950

    申请日：2016-02-15

    申请人： Renesas Electronics Corporation

    发明人： Osamu Ozawa ,  Masashi Horiguchi ,  Yuichi Okuda ,  Akihito Anzai

    IPC分类号： H03B5/32 ,  H05K1/18

    CPC分类号： H03B5/32 ,  H02H7/20 ,  H03B5/364 ,  H03B2200/0088 ,  H03B2202/03 ,  H03B2202/082 ,  H03B2202/084 ,  H05K1/181 ,  H05K2201/10075

    摘要： A wiring pattern for oscillation input signal and a wiring pattern for oscillation output signal are provided on a printed circuit board, and a wiring pattern for ground power source voltage is arranged in a region therebetween. A quartz crystal unit is connected between the wiring pattern for oscillation input signal and the wiring pattern for oscillation output signal and one ends of capacitors serving as load capacitors thereof are connected to the wiring pattern for ground power source voltage. Further, a wiring pattern for VSS is arranged so as to enclose these wiring patterns, and a wiring pattern for VSS is arranged also in a lower layer in addition thereto. By this means, reduction of a parasitic capacitance between an XIN node and an XOUT node, improvement in noise tolerance of these nodes and others can be achieved.

    摘要翻译： 用于振荡输入信号的布线图案和用于振荡输出信号的布线图案设置在印刷电路板上，并且用于接地电源电压的布线图案布置在它们之间的区域中。 在用于振荡输入信号的布线图案和振荡输出信号的布线图案之间连接石英晶体单元，并且将其作为负载电容器的电容器的一端连接到地电源电压的布线图案。 此外，为了包围这些布线图案，布置有用于VSS的布线图案，并且除此之外，还布置有用于VSS的布线图案。 通过这种方式，可以实现XIN节点和XOUT节点之间的寄生电容的减小，这些节点等的噪声容限的改善。