公开(公告)号：US09147632B2

公开(公告)日：2015-09-29

申请号：US13974488

申请日：2013-08-23

Applicant: RF Micro Devices, Inc.

Inventor： Andrew P. Ritenour

IPC: H01L23/34 ,  H01L29/66 ,  H01L29/20 ,  H01L29/778 ,  H01L23/367 ,  H01L23/482 ,  H01L29/06

CPC classification number: H01L29/66462 ,  H01L21/02378 ,  H01L21/0254 ,  H01L21/283 ,  H01L21/76898 ,  H01L23/34 ,  H01L23/3677 ,  H01L23/4824 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/2003 ,  H01L29/66431 ,  H01L29/7786 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having improved heat dissipation is disclosed. The semiconductor device includes a semi-insulating substrate and epitaxial layers disposed on the semi-insulating substrate wherein the epitaxial layers include a plurality of heat conductive vias that are disposed through the epitaxial layers with the plurality of heat conductive vias being spaced along a plurality of finger axes that are aligned generally parallel across a surface of the epitaxial layers. The semiconductor device further includes an electrode having a plurality of electrically conductive fingers that are disposed along the plurality of finger axes such that the electrically conductive fingers are in contact with the first plurality of heat conductive vias.

Abstract translation: 公开了一种具有改善的散热的半导体器件。 半导体器件包括半绝缘衬底和设置在半绝缘衬底上的外延层，其中外延层包括多个导热通孔，其布置成穿过外延层，多个导热通孔沿着多个 大致平行于外延层的表面对准的手指轴。 半导体器件还包括具有多个导电指状物的电极，沿着多个指状轴设置，使得导电指状物与第一多个导热通孔接触。

公开(公告)号：US09640632B2

公开(公告)日：2017-05-02

申请号：US14797573

申请日：2015-07-13

Applicant: RF Micro Devices, Inc.

Inventor： Andrew P. Ritenour

IPC: H01L29/66 ,  H01L23/34 ,  H01L29/20 ,  H01L21/283 ,  H01L21/768 ,  H01L21/02 ,  H01L29/778 ,  H01L23/367 ,  H01L23/482 ,  H01L29/06

CPC classification number: H01L29/66462 ,  H01L21/02378 ,  H01L21/0254 ,  H01L21/283 ,  H01L21/76898 ,  H01L23/34 ,  H01L23/3677 ,  H01L23/4824 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/2003 ,  H01L29/66431 ,  H01L29/7786 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having improved heat dissipation is disclosed. The semiconductor device includes a semi-insulating substrate and epitaxial layers disposed on the semi-insulating substrate wherein the epitaxial layers include a plurality of heat conductive vias that are disposed through the epitaxial layers with the plurality of heat conductive vias being spaced along a plurality of finger axes that are aligned generally parallel across a surface of the epitaxial layers. The semiconductor device further includes an electrode having a plurality of electrically conductive fingers that are disposed along the plurality of finger axes such that the electrically conductive fingers are in contact with the first plurality of heat conductive vias.

公开(公告)号：US20150318376A1

公开(公告)日：2015-11-05

申请号：US14797573

申请日：2015-07-13

Applicant: RF Micro Devices, Inc.

Inventor： Andrew P. Ritenour

IPC: H01L29/66 ,  H01L23/367 ,  H01L21/768 ,  H01L21/02 ,  H01L29/20 ,  H01L21/283

CPC classification number: H01L29/66462 ,  H01L21/02378 ,  H01L21/0254 ,  H01L21/283 ,  H01L21/76898 ,  H01L23/34 ,  H01L23/3677 ,  H01L23/4824 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/2003 ,  H01L29/66431 ,  H01L29/7786 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having improved heat dissipation is disclosed. The semiconductor device includes a semi-insulating substrate and epitaxial layers disposed on the semi-insulating substrate wherein the epitaxial layers include a plurality of heat conductive vias that are disposed through the epitaxial layers with the plurality of heat conductive vias being spaced along a plurality of finger axes that are aligned generally parallel across a surface of the epitaxial layers. The semiconductor device further includes an electrode having a plurality of electrically conductive fingers that are disposed along the plurality of finger axes such that the electrically conductive fingers are in contact with the first plurality of heat conductive vias.

Abstract translation: 公开了一种具有改善的散热的半导体器件。 半导体器件包括半绝缘衬底和设置在半绝缘衬底上的外延层，其中外延层包括多个导热通孔，其布置成穿过外延层，多个导热通孔沿着多个 大致平行于外延层的表面对准的手指轴。 半导体器件还包括具有多个导电指状物的电极，沿着多个指状轴设置，使得导电指状物与第一多个导热通孔接触。

公开(公告)号：US20140055192A1

公开(公告)日：2014-02-27

申请号：US13927182

申请日：2013-06-26

Applicant: RF Micro Devices, Inc.

Inventor： Andrew P. Ritenour ,  Dan Schwob

IPC: H03K17/08

CPC classification number: H03K17/08 ,  H03K17/063

Abstract: A circuit topology for limiting saturation current in power transistors is disclosed. The circuit topology includes a normally-on transistor and a normally-off transistor coupled in series. A limiter circuit is coupled between a gate of the normally-on transistor and a source of the normally-off transistor for limiting the steady-state maximum gate-to-source voltage VGS of the normally-on transistor, which in turn limits the saturation current that flows through the normally-on transistor and the normally-off transistor.

Abstract translation: 公开了用于限制功率晶体管中的饱和电流的电路拓扑。 电路拓扑包括一个常闭晶体管和一个常闭晶体管串联耦合。 限制电路耦合在常通晶体管的栅极和常关晶体管的源极之间，用于限制常导通晶体管的稳态最大栅极 - 源极电压VGS，这又限制了饱和 流经常通晶体管和常关晶体管的电流。

公开(公告)号：US09917080B2

公开(公告)日：2018-03-13

申请号：US13871526

申请日：2013-04-26

Applicant: RF Micro Devices, Inc.

Inventor： Andrew P. Ritenour

IPC: H01L29/66 ,  H01L27/06 ,  H01L27/02 ,  H01L29/778 ,  H01L29/20

CPC classification number: H01L27/0629 ,  H01L27/0248 ,  H01L29/2003 ,  H01L29/778

Abstract: A semiconductor device with electrical overstress (EOS) protection is disclosed. The semiconductor device includes a semi-insulating layer, a first contact disposed onto the semi-insulating layer, and a second contact disposed onto the semi-insulating layer. A passivation layer is disposed onto the semi-insulating layer. The passivation layer has a dielectric strength that is greater than that of the semi-insulating layer to ensure that a voltage breakdown occurs within the semi-insulating layer within a semi-insulating region between the first contact and the second contact before a voltage breakdown can occur in the passivation layer.

公开(公告)号：US09564497B2

公开(公告)日：2017-02-07

申请号：US14749274

申请日：2015-06-24

Applicant: RF Micro Devices, Inc.

Inventor： Kevin Wesley Kobayashi ,  Haldane S. Henry ,  Andrew P. Ritenour

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L29/812 ,  H01L29/417 ,  H01L29/778 ,  H01L29/20 ,  H01L29/80 ,  H01L29/16

CPC classification number: H01L29/402 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/66477 ,  H01L29/7787 ,  H01L29/80 ,  H01L29/812

Abstract: A field effect transistor having at least one structure configured to redistribute and/or reduce an electric field from gate finger ends is disclosed. Embodiments of the field effect transistor include a substrate, an active region disposed on the substrate, at least one source finger in contact with the active region, at least one drain finger in contact with the active region, and at least one gate finger in rectifying contact with the active region. One embodiment has at least one end of the at least one gate finger extending outside of the active region. Another embodiment includes at least one source field plate integral with the at least one source finger. The at least one source field plate extends over the at least one gate finger that includes a portion outside of the active region. Either embodiment can also include a sloped gate foot to further improve high voltage operation.

Abstract translation: 公开了具有至少一种结构的场效应晶体管，其被配置为重新分布和/或减少栅极指末端的电场。 场效应晶体管的实施例包括基板，设置在基板上的有源区，与有源区接触的至少一个源极指，与有源区接触的至少一个漏极指，以及整流中的至少一个栅极指 与活动区域接触。 一个实施例具有至少一个门指的至少一端延伸到有源区的外部。 另一个实施例包括与所述至少一个源手指成一体的至少一个源极场板。 所述至少一个源极场板在所述至少一个栅极指状物上延伸，所述至少一个栅极指包括有源区域外部的部分。 任何一个实施例还可以包括倾斜门脚，以进一步改善高压操作。

公开(公告)号：US09093420B2

公开(公告)日：2015-07-28

申请号：US13795986

申请日：2013-03-12

Applicant: RF Micro Devices, Inc.

Inventor： Kevin Wesley Kobayashi ,  Haldane S. Henry ,  Andrew P. Ritenour

IPC: H01L21/84 ,  H01L29/423 ,  H01L29/812 ,  H01L29/66 ,  H01L29/40 ,  H01L29/417 ,  H01L29/778 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L29/402 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/66477 ,  H01L29/7787 ,  H01L29/80 ,  H01L29/812

Abstract: Methods for fabricating a field effect transistor having at least one structure configured to redistribute and/or reduce an electric field from gate finger ends are disclosed. The methods provide field effect transistors that each include a substrate, an active region disposed on the substrate, at least one source finger in contact with the active region, at least one drain finger in contact with the active region, and at least one gate finger in rectifying contact with the active region. One embodiment has at least one end of the at least one gate finger extending outside of the active region. At least one method includes etching at least one gate channel into the passivation layer with a predetermined slope that reduces electric fields at a gate edge. Other methods include steps for fabricating a sloped gate foot, a round end, and/or a chamfered end to further improve high voltage operation.

Abstract translation: 公开了制造具有至少一种结构的场效应晶体管的方法，该结构被配置为重新分布和/或减少栅极指末端的电场。 这些方法提供场效应晶体管，其各自包括衬底，设置在衬底上的有源区，与有源区接触的至少一个源极指，与有源区接触的至少一个漏极指，以及至少一个栅极指 与活性区域整流接触。 一个实施例具有至少一个门指的至少一端延伸到有源区的外部。 至少一种方法包括以预定斜率将至少一个栅极通道蚀刻到钝化层中，该斜率减小栅极边缘处的电场。 其他方法包括用于制造倾斜门脚，圆端和/或倒角端的步骤，以进一步改善高压操作。

公开(公告)号：US20140054604A1

公开(公告)日：2014-02-27

申请号：US13974488

申请日：2013-08-23

Applicant: RF Micro Devices, Inc.

Inventor： Andrew P. Ritenour

IPC: H01L23/34 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/66462 ,  H01L21/02378 ,  H01L21/0254 ,  H01L21/283 ,  H01L21/76898 ,  H01L23/34 ,  H01L23/3677 ,  H01L23/4824 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/2003 ,  H01L29/66431 ,  H01L29/7786 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having improved heat dissipation is disclosed. The semiconductor device includes a semi-insulating substrate and epitaxial layers disposed on the semi-insulating substrate wherein the epitaxial layers include a plurality of heat conductive vias that are disposed through the epitaxial layers with the plurality of heat conductive vias being spaced along a plurality of finger axes that are aligned generally parallel across a surface of the epitaxial layers. The semiconductor device further includes an electrode having a plurality of electrically conductive fingers that are disposed along the plurality of finger axes such that the electrically conductive fingers are in contact with the first plurality of heat conductive vias.

Abstract translation: 公开了一种具有改善的散热的半导体器件。 半导体器件包括半绝缘衬底和设置在半绝缘衬底上的外延层，其中外延层包括多个导热通孔，其布置成穿过外延层，多个导热通孔沿着多个 大致平行于外延层的表面对准的手指轴。 半导体器件还包括具有多个导电指状物的电极，沿着多个指状轴设置，使得导电指状物与第一多个导热通孔接触。

公开(公告)号：US20140054585A1

公开(公告)日：2014-02-27

申请号：US13973482

申请日：2013-08-22

Applicant: RF Micro Devices, Inc.

Inventor： Andrew P. Ritenour

IPC: H01L27/02

CPC classification number: H01L27/0248 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/41775 ,  H01L29/778 ,  H01L29/861

Abstract: A lateral semiconductor device having a vertical region for providing a protective avalanche breakdown (PAB) is disclosed. The lateral semiconductor device has a lateral structure that includes a conductive substrate, semi-insulating layer(s) disposed on the conductive substrate, device layer(s) disposed on the semi-insulating layer(s), along with a source electrode and a drain electrode disposed on the device layer(s). The vertical region is separated from the source electrode by a lateral region wherein the vertical region has a relatively lower breakdown voltage level than a relatively higher breakdown voltage level of the lateral region for providing the PAB within the vertical region to prevent a potentially damaging breakdown of the lateral region. The vertical region is structured to be more rugged than the lateral region and thus will not be damaged by a PAB event.

Abstract translation: 公开了具有用于提供保护性雪崩击穿（PAB）的垂直区域的横向半导体器件。 横向半导体器件具有横向结构，其包括导电衬底，设置在导电衬底上的半绝缘层，设置在半绝缘层上的器件层以及源电极和 漏电极设置在器件层上。 垂直区域通过横向区域与源极分离，其中垂直区域具有比用于在垂直区域内提供PAB的相对较高的击穿电压电平相对较低的击穿电压电平，以防止潜在的破坏性破坏 侧面区域。 垂直区域被构造成比横向区域更坚固，因此不会被PAB事件损坏。

公开(公告)号：US09455327B2

公开(公告)日：2016-09-27

申请号：US14731736

申请日：2015-06-05

Applicant: RF Micro Devices, Inc.

Inventor： Andrew P. Ritenour

IPC: H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L29/423 ,  H01L29/78 ,  H01L29/10 ,  H01L29/20 ,  H01L29/47 ,  H01L29/778 ,  H01L29/812 ,  H01L29/49

CPC classification number: H01L29/517 ,  H01L21/28264 ,  H01L29/1054 ,  H01L29/2003 ,  H01L29/42364 ,  H01L29/475 ,  H01L29/4958 ,  H01L29/518 ,  H01L29/778 ,  H01L29/78 ,  H01L29/812

Abstract: A Schottky gated transistor having reduced gate leakage current is disclosed. The Schottky gated transistor includes a substrate and a plurality of epitaxial layers disposed on the substrate. Further included is a gate contact having an interfacial layer disposed on a surface of the plurality of epitaxial layers and having a thickness that is between about 5 Angstroms (Å) and 40 Å. The interfacial layer can be made up of non-native materials in contrast to a native insulator such as silicon dioxide (SiO2) that is used as an insulating gate layer with silicon-based power transistors. The Schottky gated transistor further includes at least one metal layer disposed over the interfacial layer. A source contact and a drain contact are disposed on the surface of the plurality of epitaxial layers, wherein the source contact and the drain contact are spaced apart from the gate contact and each other.

Abstract translation: 公开了一种具有降低的栅极漏电流的肖特基门控晶体管。 肖特基门控晶体管包括衬底和设置在衬底上的多个外延层。 进一步包括的门接触件具有设置在多个外延层的表面上并具有介于约5埃（埃）和40埃之间的厚度的界面层。 与天然绝缘体（例如用作具有硅基功率晶体管的绝缘栅极层的二氧化硅（SiO 2））相比，界面层可以由非天然材料构成。 肖特基门控晶体管还包括设置在界面层上的至少一个金属层。 源极触点和漏极触点设置在多个外延层的表面上，其中源极触点和漏极触点与栅极触点和彼此间隔开。