-
1.发明授权Method and apparatus for reducing switching noise in a system-on-chip (SoC) integrated circuit including an analog-to-digital converter (ADC) 有权包括模数转换器（ADC）在片上系统（SoC）集成电路中降低开关噪声的方法和装置，公开(公告)号：US07515076B1
公开(公告)日：2009-04-07
申请号：US11864876
申请日：2007-09-28
申请人： Rahul Singh , Prashanth Drakshapalli , Jie Fang , Edwin De Angel , Mohit Sood
发明人： Rahul Singh , Prashanth Drakshapalli , Jie Fang , Edwin De Angel , Mohit Sood
IPC分类号： H03M1/00
摘要： A method and apparatus for reducing switching noise in a system-on-chip (SoC) integrated circuit including an analog to digital converter (ADC) provides for reduced noise in the ADC conversions. Sampling circuits of the ADC are operated by sampling clock signals and digital circuits and other noise-generating circuits such as power converters, are operated by digital circuit clock signals. Both sets of clock signals are derived from the same master clock by a clock generator circuit, but an offset is applied in the clock generator circuit to move the edges of the digital circuit clock signals away from critical sampling intervals corresponding to edges of the sampling clocks. In one embodiment, the offset is applied by a processor core that forms part of the digital circuits by setting a value in the clock generator, which the clock generator then loads into the divider after halting the clock to the digital circuits.
摘要翻译： 包括模数转换器（ADC）在内的片上系统（SoC）集成电路中降低开关噪声的方法和装置提供了ADC转换中降低的噪声。 ADC的采样电路通过采样时钟信号进行操作，数字电路和其他噪声发生电路（如电源转换器）由数字电路时钟信号进行操作。 这两组时钟信号由时钟发生器电路从相同的主时钟导出，但是在时钟发生器电路中施加偏移以使数字电路时钟信号的边缘远离对应于采样时钟的边缘的关键采样间隔 。 在一个实施例中，通过设置时钟发生器中的值来构成数字电路的一部分的处理器内核施加偏移，时钟发生器在暂停数字电路的时钟之后将其加载到分频器中。
-
2.发明授权公开(公告)号：US08165835B1
公开(公告)日：2012-04-24
申请号：US12259112
申请日：2008-10-27
申请人： Rahul Singh , Dale Brummel , Hang Liu , Robert Leon Gorsegner , Edwin De Angel , Jean Charles Pina
发明人： Rahul Singh , Dale Brummel , Hang Liu , Robert Leon Gorsegner , Edwin De Angel , Jean Charles Pina
CPC分类号： G01R21/1331
摘要： A power measurement and calibration system provides power and line frequency measurements by using a bandpass filter having complex voltage and current outputs from which real and imaginary power components can be determined. Calibration of the filter may be omitted if a complex wavelet filter is used to implement the bandpass filter and a determination of line frequency can also be provided for downstream use. A processor receiving data from the output of the filter can compute real and imaginary power, power factor and the line frequency. The filter may be implemented by a processor executing program instructions, or a digital circuit implementing the filter and optionally a CORDIC rotator for computing the current-to-voltage phase relationship can provide input to the processor for power measurement and calibration of the sample rate to line frequency relationship and for other uses.
摘要翻译： 功率测量和校准系统通过使用具有复数电压和电流输出的带通滤波器来提供功率和线路频率测量，从而可以确定实际和虚拟功率分量。 如果使用复小波滤波器来实现带通滤波器，则也可以省略滤波器的校准，还可以为下游使用提供线路频率的确定。 从滤波器的输出接收数据的处理器可以计算实际功率，虚功率，功率因数和线路频率。 滤波器可以由执行程序指令的处理器或实现滤波器的数字电路和可选地用于计算电流到电压相位关系的CORDIC转子来实现，其可以向处理器提供输入以进行功率测量并将采样率校准到 线频率关系和其他用途。
-
3.发明授权Method and apparatus for automatically securing non-volatile (NV) storage in an integrated circuit 有权在集成电路中自动保护非易失性（NV）存储的方法和装置公开(公告)号：US07657722B1
公开(公告)日：2010-02-02
申请号：US11772136
申请日：2007-06-30
IPC分类号： G06F12/00
摘要： A method and apparatus for automatically securing non-volatile (NV) storage in an integrated circuit provides improved resistance to code copying and reverse-engineering attacks. External interfaces that provide read access to the NV storage are be disabled, for a predetermined time after a reset or other initialization signal is received. An internal lock state bit or key is checked as well as an external lock prevent indication. If the lock prevent indication is not received, or the internal lock state bit is already set, then the integrated circuit is operated under a locked condition, in which external access to the NV storage values is prevented. The lock prevent indication may be a signal provided during reset of the integrated circuit on a terminal that is used for another purpose after initialization of the integrated circuit.
摘要翻译： 用于在集成电路中自动保护非易失性（NV）存储的方法和装置提供了改进的对代码复制和逆向工程攻击的抵抗力。 在接收到复位或其他初始化信号之后的预定时间内，禁止提供对NV存储器的读取访问的外部接口。 检查内部锁定状态位或键以及外部锁定防止指示。 如果没有接收到锁定防止指示，或内部锁定状态位已设置，则集成电路在锁定状态下运行，从而防止NV存储值的外部访问。 锁定防止指示可以是在集成电路初始化之后用于另一目的的终端上的集成电路复位期间提供的信号。
-
公开(公告)号：US06183122B2
公开(公告)日：2001-02-06
申请号：US08923132
申请日：1997-09-04
申请人： Edwin De Angel
发明人： Edwin De Angel
IPC分类号： G06F750
CPC分类号： G06F7/5332 , G06F7/49994
摘要： A digital parallel multiplier having encoders for each segmented bit pair of the multiplier input data and which selects one of 4 coefficients, based on the sum of the bit pair, that are then applied to the multiplicand input data to form a plurality of factored multiplicands. The sum of the factored multiplicands is augmented by two additional bits for all but the last of the factored multiplicands and by a logic 1 bit. The two additional bits are a logic 1 followed by the inverse of the sign bit of the factored multiplicand and are placed in the next two significant bit positions after the sign bit of the factored multiplicand, and the logic 1 is in the position occupied by the sign bit of the factored multiplicands which has the least significant bit position of all of the sign bits of the factored multiplicands.
摘要翻译： 数字并行乘法器具有用于乘法器输入数据的每个分段比特对的编码器，并且基于比特对的和来选择4个系数中的一个，然后将其应用于被乘数输入数据以形成多个因子被乘数。 除以最后一个因子被乘数和逻辑1位之外，所有因子的被乘数之和都增加了两个附加位。 两个附加位是逻辑1，后面是因式被乘数的符号位的倒数，并且被置于比因子被乘数的符号位之后的下两个有效位位置，并且逻辑1位于由 具有因子被乘数的所有符号位的最低有效位位置的因式被乘数的符号位。
-
5.发明授权Application of a conditionally stable instrumentation amplifier to industrial measurement 有权将有条件稳定的仪表放大器应用于工业测量公开(公告)号：US06525589B1
公开(公告)日：2003-02-25
申请号：US09695705
申请日：2000-10-25
申请人： Axel Thomsen , Edwin De Angel , Sherry Wu , Aryesh Amar , Jerome E. Johnston
发明人： Axel Thomsen , Edwin De Angel , Sherry Wu , Aryesh Amar , Jerome E. Johnston
IPC分类号： H03K1716
摘要： An instrumentation circuit has an integrated circuit that has input terminals, an amplifier arrangement using feed forward compensation and an analog to digital converter and a serial data output receiving the output from said amplifier arrangement. A bridge circuit, having a transducer, or a thermocouple arrangement are connected to input terminals of the integrated circuit.
摘要翻译： 仪表电路具有具有输入端子的集成电路，使用前馈补偿的放大器装置和模数转换器以及接收来自所述放大器装置的输出的串行数据输出。 具有换能器或热电偶布置的桥式电路连接到集成电路的输入端子。
-
公开(公告)号：US06337636B1
公开(公告)日：2002-01-08
申请号：US09153867
申请日：1998-09-16
申请人： Joel Page , Edwin De Angel , Wai Laing Lee , Lei Wang , Hong Helena Zheng , Chung-Kai Chow
发明人： Joel Page , Edwin De Angel , Wai Laing Lee , Lei Wang , Hong Helena Zheng , Chung-Kai Chow
IPC分类号： G08C1508
CPC分类号： H03H17/0288 , G01V1/22 , G01V1/26
摘要： A data acquisition system has a central station connected to a plurality of nodes over a network. Each node is connected to receive signals from one or more sensors ad each is configured to have substantially the same transmission delay to said central station. The central station is configured to notify all nodes of an event time at which a data event, such as a seismic shot, occurred.
摘要翻译： 数据采集系统具有通过网络连接到多个节点的中心站。 每个节点被连接以从一个或多个传感器接收信号，每个传感器被配置为具有与所述中心站基本上相同的传输延迟。 中心站被配置为通知所有节点发生诸如地震拍摄的数据事件的事件时间。
-
公开(公告)号：US06317765B1
公开(公告)日：2001-11-13
申请号：US09153862
申请日：1998-09-16
申请人： Joel Page , Edwin De Angel , Wai Laing Lee , Lei Wang , Hong Helena Zheng , Chung-Kai Chow
发明人： Joel Page , Edwin De Angel , Wai Laing Lee , Lei Wang , Hong Helena Zheng , Chung-Kai Chow
IPC分类号： G06F1717
CPC分类号： H03H17/0282 , H03H17/0226 , H03H17/0664
摘要： A decimation filter implements selective decimation ratios by arranging a plurality of sinc filters in different pipeline arrangements to produce the desired ratio. Power savings area achieved by implementing the sinc filters as FIR sinc filters and by implementing multiplications using look up tables. One approach uses a fixed first stage filter and one or more second stage sinc filters selected from the group comprising two 4th order, 5 tap sinc filters, a 4th order, 9 tap sinc filter; a 5th order, 6 tap sinc filter and a 6th order 7 tap sinc filter. The sinc filter is particularly useful applications in the field of data acquisition and particularly in the area of seismic sensing.
摘要翻译： 抽取滤波器通过在不同的流水线布置中布置多个正弦滤波器来实现选择性抽取比，以产生期望的比率。 通过将sinc滤波器实现为FIR sinc滤波器并通过使用查找表来实现乘法而实现的省电区域。 一种方法使用固定的第一级滤波器和一个或多个第二级sinc滤波器，其选自包括两个4阶，5抽头sinc滤波器，第4级，9抽头sinc滤波器的组; 5号，6抽头sinc过滤器和6阶7抽头sinc过滤器。 sinc滤波器在数据采集领域尤其是在地震检测领域尤其有用。
-
公开(公告)号：US06243733B1
公开(公告)日：2001-06-05
申请号：US09153868
申请日：1998-09-16
申请人： Joel Page , Edwin De Angel , Wai Laing Lee , Lei Wang , Hong Helena Zheng , Chung-Kai Chow
发明人： Joel Page , Edwin De Angel , Wai Laing Lee , Lei Wang , Hong Helena Zheng , Chung-Kai Chow
IPC分类号： G06F738
CPC分类号： G06F7/5443 , G06F7/49947
摘要： A multiply add carry (MAC) circuit correctly determines the value of a carry bit when an operation X*Y+Z is undertaken, where X, Y and Z are real numbers and where an accumulator and rounding are utilized. The circuit (1) determines if the product X*Y is negative, (2) determines if the value in the accumulator is negative, (3) determines if a round bit propagates all the way to the most significant bit (MSB) position, (4) determines if the result X*Y+Accumulator+round is negative; and (5) determines a correct carry bit based on the other determinations.
摘要翻译： 当进行X * Y + Z操作时，乘法加法（MAC）电路正确地确定进位位的值，其中X，Y和Z是实数，并且使用累加器和舍入。 电路（1）确定乘积X * Y是否为负，（2）确定累加器中的值是否为负，（3）确定一个圆比特是否一直传播到最高有效位（MSB）位置， （4）确定结果X * Y +累加器+圆是否为负; 和（5）基于其他确定来确定正确的进位位。
-
公开(公告)号：US6085214A
公开(公告)日：2000-07-04
申请号：US923693
申请日：1997-09-04
申请人： Edwin De Angel
发明人： Edwin De Angel
IPC分类号： G06F7/52
CPC分类号： G06F7/5338
摘要： A digital parallel multiplier having encoders for each segmented bit pair of the multiplier input data and which selects one of 4 coefficients, based on the sum of the bit pair, that are then applied to the multiplicand input data. When a 3X coefficient of the multiplicand input data is to be generated, a -1 coefficient is output by the encoder requiring the 3X coefficient, and a 1 is added to the sum of the next most significant bit pair.
摘要翻译： 数字并行乘法器具有用于乘法器输入数据的每个分段比特对的编码器，并且基于比特对的和来选择4个系数中的一个，然后将其应用于被乘数输入数据。 当要产生被乘数输入数据的3X系数时，需要3X系数的编码器输出-1系数，并将1加到下一个最高有效位对之和。
-
公开(公告)号：US07218612B2
公开(公告)日：2007-05-15
申请号：US10457113
申请日：2003-06-09
申请人： Joel Page , Edwin De Angel , Wai Laing Lee , Lei Wang , Hong Helena Zheng , Chung-Kai Chow
发明人： Joel Page , Edwin De Angel , Wai Laing Lee , Lei Wang , Hong Helena Zheng , Chung-Kai Chow
CPC分类号： H04J3/0682 , G01V1/22
摘要： A network arrangement uses a poll select control protocol and a loop back arrangement at each node for equalizing transmission delay from each node to a central station. Delays at each node can be adjusted to start timing in response to a broadcast signal indicating an amount of delay to be applied from the start of a synchronization interval to the beginning of transmission of data collected at the nodes. The arrangement is particularly useful in the field of data acquisition and particularly in the area of seismic sensing.
摘要翻译： 网络布置在每个节点处使用轮询选择控制协议和循环布置来均衡从每个节点到中心站的传输延迟。 可以调整每个节点的延迟以响应于指示从同步间隔开始到在节点处收集的数据的传输的开始而应用的延迟量的广播信号。 该方案在数据采集领域尤其在地震检测领域特别有用。
-
-
-
-
-
-
-
-
-
搜索结果
21 条记录 (耗时 0.031 秒)