公开(公告)号：US06372544B1

公开(公告)日：2002-04-16

申请号：US09599530

申请日：2000-06-23

申请人： Jonathan D. Halderman ,  Raj N. Master

发明人： Jonathan D. Halderman ,  Raj N. Master

IPC分类号： H01L2144

CPC分类号： H01L21/563 ,  H01L24/31 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83859 ,  H01L2224/83951 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/05599

摘要： A softened and compliant fillet portion of a cured polymeric underfill in a flip-chip arrangement reduces occurences of fillet crackings caused by thermal stresses. The softening of the fillet is achieved by chemically breaking cross-links in the cured polymeric underfill material using a chemical solvent. In another embodiment, the softening of the fillet is achieved by applying heat using a controllable beam of thermal energy to break up the cross-links to thereby soften the fillet.

摘要翻译： 固化的聚合物底部填充物的软化且柔顺的圆角部分以倒装芯片布置减少了由热应力引起的圆角裂纹的发生。 通过使用化学溶剂化学破坏固化的聚合物底部填充材料中的交联来实现圆角的软化。 在另一个实施例中，通过使用可控的热能束施加热来实现圆角的软化，以分解交联以便软化圆角。

公开(公告)号：US06709963B1

公开(公告)日：2004-03-23

申请号：US09617104

申请日：2000-07-14

申请人： Jonathan D. Halderman ,  Raj N. Master

发明人： Jonathan D. Halderman ,  Raj N. Master

IPC分类号： H01L2144

CPC分类号： H01L24/11 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30107 ,  H05K3/3436 ,  H05K3/3489 ,  H01L2924/00 ,  H01L2224/0401

摘要： A method and an apparatus are provided for selectively depositing flux on a plurality of flip-chip bumps arranged on a semiconductor chip by jet printing a flux pattern, which is substantially identical to the arrangement pattern of the flip-chip bumps. The flux pattern is determined by measuring the chip configuration and converting the configuration to computer-recognizable data. The converted chip configuration is stored in data storage, and a jet printing head prints the flux pattern based on the computer-recognizable data. A conveyance plate is provided to transport the semiconductor chip to a flux-deposition area below the jet printing head.

摘要翻译： 提供了一种方法和装置，用于通过喷射打印基本上与倒装芯片凸块的布置图案相同的磁通图案，在布置在半导体芯片上的多个倒装芯片凸块上选择性地沉积磁通。 通过测量芯片配置并将配置转换为计算机可识别的数据来确定通量模式。 转换的芯片配置存储在数据存储器中，并且喷墨打印头基于计算机可识别的数据打印通量图案。 提供传送板以将半导体芯片传送到喷墨打印头下方的助熔剂区域。

公开(公告)号：US06536649B1

公开(公告)日：2003-03-25

申请号：US09627437

申请日：2000-07-28

申请人： Raj N. Master ,  Jonathan D. Halderman

发明人： Raj N. Master ,  Jonathan D. Halderman

IPC分类号： B23R3704

CPC分类号： H01L21/67253

摘要： Residue contaminates semiconductor devices during processing in a furnace. Residue contamination is prevented by removing the residue before it builds up to a point where it can contaminate semiconductor devices. Residue build-up is monitored using a residue build-up monitoring device mounted on the furnace exhaust stack. When residue build-up reaches a predetermined level a signal is generated by the residue build-up monitoring device notifying technicians that furnace cleaning is required.

摘要翻译： 残渣在炉中加工期间污染半导体器件。 通过在残留物积聚到可能污染半导体器件的点之前去除残留物来防止残留污染。 使用安装在炉排气堆上的残渣积聚监测装置来监测残留物积聚。 当残渣累积达到预定水平时，残留物积聚监测装置产生信号，通知技术人员需要进行炉清洗。

公开(公告)号：US06258612B1

公开(公告)日：2001-07-10

申请号：US09642832

申请日：2000-08-22

申请人： Raj N. Master ,  Jonathan D. Halderman

发明人： Raj N. Master ,  Jonathan D. Halderman

IPC分类号： H01L2166

CPC分类号： H01L22/20 ,  H01L24/81 ,  H01L2224/13111 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  Y10S33/04 ,  H01L2924/00

摘要： A package assembly is formed by applying flux to a device and/or a substrate and inspecting the applied flux to determine whether the amount applied is within a predetermined range. Embodiments include applying a rosin based flux on a laminate substrate and measuring the thickness of the applied flux with an interferometer.

摘要翻译： 通过将助焊剂施加到装置和/或基底并检查所施加的通量以确定所施加的量是否在预定范围内来形成包装组件。 实施方案包括在层压基板上施加松香基焊剂并用干涉仪测量施加的焊剂的厚度。

公开(公告)号：US06367679B1

公开(公告)日：2002-04-09

申请号：US09642831

申请日：2000-08-22

申请人： Raj N. Master ,  Jonathan D. Halderman

发明人： Raj N. Master ,  Jonathan D. Halderman

IPC分类号： B23K3112

CPC分类号： B23K3/029 ,  H05K3/26

摘要： Detection of flux residue remaining the formation of a device/substrate assembly is carried out by contacting the assembly with a fixed amount of solvent adapted to remove residual flux from the assembly and measuring the conductivity or resistance of the contacted solvent to determine the presence of flux residue in the solvent obtained from the assembly. Embodiments include contacting the assembly with isopropanol by immersing and withdrawing the assembly in a fixed amount of the solvent and measuring the conductivity of the contacted solvent with a volt meter.

摘要翻译： 通过使组件与固定量的溶剂接触来检测剩余的器件/衬底组件的形成，该溶剂适于从组件中除去残留的焊剂并测量接触溶剂的导电性或电阻以确定焊剂的存在 残留在从组装得到的溶剂中。 实施方案包括通过将组件浸入和取出固定量的溶剂并用电压表测量接触溶剂的电导率来使组件与异丙醇接触。

公开(公告)号：US07923850B2

公开(公告)日：2011-04-12

申请号：US12198227

申请日：2008-08-26

申请人： Mohammad Khan ,  Jun Zhai ,  Ranjit Gannamani ,  Raj N. Master

发明人： Mohammad Khan ,  Jun Zhai ,  Ranjit Gannamani ,  Raj N. Master

IPC分类号： H01L23/448 ,  H01L21/56

CPC分类号： H01L23/16 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/562 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/0401

摘要： Various semiconductor chip arrangements and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a semiconductor chip that has an external peripheral wall to a first side of a substrate. A first metallic ring is coupled to the first side of the substrate. The first metallic ring has an internal peripheral wall that frames the semiconductor chip and is separated from the external peripheral wall by a gap. The first metallic ring has a coefficient of thermal expansion less than about 6.0 10−6 K−1.

摘要翻译： 公开了各种半导体芯片布置及其制造方法。 一方面，提供一种制造方法，其包括将具有外周壁的半导体芯片与基板的第一侧耦合。 第一金属环耦合到衬底的第一侧。 第一金属环具有框架半导体芯片并且与外周壁隔开间隙的内周壁。 第一金属环的热膨胀系数小于约6.0×10 -6 K -1。

公开(公告)号：US20080227310A1

公开(公告)日：2008-09-18

申请号：US11687529

申请日：2007-03-16

申请人： Seah Sun Too ,  Raj N. Master ,  Jacquana Diep ,  Mohammad Khan

发明人： Seah Sun Too ,  Raj N. Master ,  Jacquana Diep ,  Mohammad Khan

IPC分类号： H01R12/00

CPC分类号： H01L23/433 ,  H01L23/467 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/16152 ,  H01L2924/3511 ,  H01R12/7076 ,  H05K7/1061 ,  H01L2224/0401

摘要： Various sockets for packaged integrated circuits and methods of making the same are provided. In one aspect, a method of mounting a semiconductor chip is provided that includes providing a package that has a base substrate with a first side and a second side opposite the first side. The second side has a central region. The package includes a semiconductor chip and a lid coupled to the first side. A socket is provided for receiving the base substrate. The socket includes a mound that projects toward the second side of the base substrate when the base substrate is seated in the socket to provide support for the central region of the base substrate. The package is mounted in the socket. The mound provides support for the central region of the base substrate.

摘要翻译： 提供了用于封装集成电路的各种插座及其制造方法。 一方面，提供了一种安装半导体芯片的方法，其包括提供具有第一侧和与第一侧相对的第二侧的基底的封装。 第二边有一个中部地区。 该封装包括半导体芯片和连接到第一侧的盖子。 提供了用于接收基底的插座。 插座包括当基底座位于插座中时朝向基底基板的第二侧突出的墩，以为基底基板的中心区域提供支撑。 包装安装在插座中。 土丘为基底的中心区域提供支撑。

公开(公告)号：US5543584A

公开(公告)日：1996-08-06

申请号：US843684

申请日：1992-02-28

申请人： Edward F. Handford ,  Joseph M. Harvilchuck ,  Mario J. Interrante ,  Raymond A. Jackson ,  Raj N. Master ,  Sudipta K. Ray ,  William E. Sablinski ,  Thomas A. Wassick

发明人： Edward F. Handford ,  Joseph M. Harvilchuck ,  Mario J. Interrante ,  Raymond A. Jackson ,  Raj N. Master ,  Sudipta K. Ray ,  William E. Sablinski ,  Thomas A. Wassick

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L23/498 ,  H01L23/52 ,  H01L23/525 ,  H01L23/538 ,  H05K3/00 ,  H05K3/02 ,  H05K3/22 ,  H05K3/34 ,  H05K1/11

CPC分类号： H01L21/76892 ,  H01L23/49866 ,  H01L23/525 ,  H05K3/225 ,  H01L2924/0002 ,  H05K2201/10181 ,  H05K2201/10234 ,  H05K2201/1028 ,  H05K2201/10287 ,  H05K2203/0769 ,  H05K2203/107 ,  H05K2203/121 ,  H05K2203/173 ,  H05K2203/175 ,  H05K3/0017 ,  H05K3/027 ,  H05K3/34 ,  Y10T29/49124

摘要： The present invention relates generally to a new method of repairing electrical lines, and more particularly to repairing electrical lines having an opening at the module level with devices in place. Various methods and processes are used to repair this open or defective portion in an electrical conductor line. It could be repaired by securing a jumper wire or nugget across the open or the repair could be made by a deposition process, which includes but is not limited to filling the opening with a solder type material or inserting a solder coated electrical wire and heating the solder and allowing the solder to melt and repair the open. One of the attributes of this invention is the ability to repair on a substrate or module on which active components such as chips, and passive components such as pins, capacitors, etc. have been attached. The invention also allows repair of fine line patterns which are normally not repairable by conventional techniques.

摘要翻译： 本发明一般涉及一种修复电线的新方法，更具体地说，涉及在装置的适当位置修复具有模块级开口的电线。 使用各种方法和过程来修复电导体线中的这个开路或有缺陷的部分。 它可以通过将跨接线或熔核固定在整个开口处进行修复，或者可以通过沉积工艺进行修复，该沉积工艺包括但不限于用焊料型材料填充开口或插入焊料涂覆的电线并加热 焊接并允许焊料熔化并修复开路。 本发明的一个特征是在其上附着有诸如引脚，电容器等的诸如芯片和无源部件的有源部件的基板或模块上进行修复的能力。 本发明还允许修复通常不能通过常规技术修复的细线图案。

公开(公告)号：US4234367A

公开(公告)日：1980-11-18

申请号：US23112

申请日：1979-03-23

申请人： Lester W. Herron ,  Raj N. Master ,  Rao R. Tummala

发明人： Lester W. Herron ,  Raj N. Master ,  Rao R. Tummala

IPC分类号： H05K3/46 ,  C03C10/00 ,  C03C27/00 ,  H01L21/48 ,  H01L23/52 ,  H05K1/00 ,  H05K1/03 ,  B32B31/24 ,  C03B32/00 ,  C04B39/00

CPC分类号： C03C10/0045 ,  C03C10/00 ,  C03C27/00 ,  H01L21/4807 ,  H01L21/4867 ,  H01L2924/01078 ,  H05K1/0306 ,  H05K3/4629 ,  H05K3/4676

摘要： The formation of sintered glass-ceramic substrates containing multi-level, interconnected thick-film circuit patterns of copper-based conductors obtained by firing in a controlled ambient of hydrogen and H.sub.2 O at temperatures below the melting point of copper.

摘要翻译： 形成烧结的玻璃 - 陶瓷衬底，其包含铜基导体的多层互连厚膜电路图案，其通过在低于铜熔点的温度下在受控环境的氢气和H 2 O中进行烧制获得。

公开(公告)号：US20080124841A1

公开(公告)日：2008-05-29

申请号：US11462993

申请日：2006-08-07

申请人： Seah Sun Too ,  Raj N. Master ,  Jacquana Diep ,  Mohammad Khan

发明人： Seah Sun Too ,  Raj N. Master ,  Jacquana Diep ,  Mohammad Khan

IPC分类号： H01L21/58

CPC分类号： H01L23/10 ,  H01L24/32 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/16152 ,  H01L2924/166 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/0401

摘要： Various method and apparatus for packaging an integrated circuit are provided. In one aspect, a method of packaging an integrated circuit is provided that includes coupling an integrated circuit to a substrate, mixing an adhesive with a plurality of particles, and coupling a lid to the substrate with the adhesive. At least a portion of the plurality of particles in the adhesive oppose compressive force from the lid to restrict rotation of the lid relative to the substrate.

摘要翻译： 提供了用于封装集成电路的各种方法和装置。 一方面，提供一种封装集成电路的方法，其包括将集成电路耦合到基板，将粘合剂与多个颗粒混合，以及用盖子将盖子与粘合剂连接。 粘合剂中多个颗粒的至少一部分与来自盖的压缩力相反，以限制盖相对于基底的旋转。