公开(公告)号：US20090219100A1

公开(公告)日：2009-09-03

申请号：US12040875

申请日：2008-03-01

申请人： Rajasekhar Pullela ,  Morten Damgaard ,  Shahrzad Tadjpour ,  John E. Vasa ,  Hoon Lee

发明人： Rajasekhar Pullela ,  Morten Damgaard ,  Shahrzad Tadjpour ,  John E. Vasa ,  Hoon Lee

IPC分类号： G01R23/00

CPC分类号： H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0991

摘要： A phase-locked loop (PLL) is arranged to receive high-pass data at a first input and low-pass data at a second input. A first digital input is coupled to a primary path through a digital-to-analog converter (DAC) and a second digital input is coupled to a feedback path of the PLL. The controller provides the first input and the second input during a calibration procedure. The controller adjusts first and second control inputs in an attempt to keep the input voltage to a voltage-controlled oscillator (VCO) in the PLL constant while determining the gain of the VCO in Hz/LSB.

摘要翻译： 锁相环（PLL）被布置成在第一输入处接收高通数据并在第二输入端接收低通数据。 第一数字输入通过数模转换器（DAC）耦合到主路径，并且第二数字输入耦合到PLL的反馈路径。 控制器在校准过程中提供第一个输入和第二个输入。 控制器调整第一和第二控制输入，试图将输入电压保持为PLL中的压控振荡器（VCO），同时以Hz / LSB确定VCO的增益。

公开(公告)号：US07612617B2

公开(公告)日：2009-11-03

申请号：US12040875

申请日：2008-03-01

申请人： Rajasekhar Pullela ,  Morten Damgaard ,  Shahrzad Tadjpour ,  John E. Vasa ,  Hoon Lee

发明人： Rajasekhar Pullela ,  Morten Damgaard ,  Shahrzad Tadjpour ,  John E. Vasa ,  Hoon Lee

IPC分类号： H03L7/099 ,  H03L7/18

CPC分类号： H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0991

摘要： A phase-locked loop (PLL) is arranged to receive high-pass data at a first input and low-pass data at a second input. A first digital input is coupled to a primary path through a digital-to-analog converter (DAC) and a second digital input is coupled to a feedback path of the PLL. The controller provides the first input and the second input during a calibration procedure. The controller adjusts first and second control inputs in an attempt to keep the input voltage to a voltage-controlled oscillator (VCO) in the PLL constant while determining the gain of the VCO in Hz/LSB.

摘要翻译： 锁相环（PLL）被布置成在第一输入处接收高通数据并在第二输入端接收低通数据。 第一数字输入通过数模转换器（DAC）耦合到主路径，并且第二数字输入耦合到PLL的反馈路径。 控制器在校准过程中提供第一个输入和第二个输入。 控制器调整第一和第二控制输入，试图将输入电压保持为PLL中的压控振荡器（VCO），同时以Hz / LSB确定VCO的增益。

公开(公告)号：US20080051042A1

公开(公告)日：2008-02-28

申请号：US11510465

申请日：2006-08-25

申请人： Jaleh Komaili ,  John E. Vasa ,  Morten Damgaard ,  David S. Ripley

发明人： Jaleh Komaili ,  John E. Vasa ,  Morten Damgaard ,  David S. Ripley

IPC分类号： H04B1/04

CPC分类号： H04B1/0475 ,  H03F1/3241 ,  H03F1/3288 ,  H03F3/195 ,  H03F3/24 ,  H03F2201/3233 ,  H04B2001/0425

摘要： An adaptive predistortion system for controlling an open loop power amplifier includes a transmitter, a receiver, a phase and amplitude determination element configured to determine amplitude and phase characteristics of an output signal generated in the transmitter, the signal representing transmitter characteristics, an amplitude resampling element configured to generate an updated AM-AM predistortion signal based on the output signal generated in the transmitter, and an amplitude predistortion element configured to compare the updated AM-AM predistortion signal with a factory-calibrated AM-AM predistortion signal and generate an amplitude compensation signal. The adaptive predistortion system also includes a phase comparison element configured to compare the signal representing transmitter characteristics with a desired phase signal, a phase resampling element configured to generate an updated AM-PM predistortion signal based on the output signal generated in the transmitter, and a phase predistortion element configured to compare the updated AM-PM predistortion signal with a factory-calibrated AM-PM predistortion signal and generate a phase compensation signal.

摘要翻译： 用于控制开环功率放大器的自适应预失真系统包括发射机，接收机，相位和幅度确定元件，其被配置为确定在发射机中产生的输出信号的幅度和相位特性，表示发射机特性的信号，幅度重采样元件 被配置为基于在所述发射机中产生的输出信号产生更新的AM-AM预失真信号，以及幅度预失真元件，其被配置为将所述更新的AM-AM预失真信号与出厂校准的AM-AM预失真信号进行比较，并产生振幅补偿 信号。 自适应预失真系统还包括相位比较元件，其被配置为将表示发射机特性的信号与期望的相位信号进行比较;相位重采样元件，被配置为基于在发射机中产生的输出信号生成更新的AM-PM预失真信号，以及 相位预失真元件，被配置为将更新的AM-PM预失真信号与出厂校准的AM-PM预失真信号进行比较，并产生相位补偿信号。

公开(公告)号：US07187314B1

公开(公告)日：2007-03-06

申请号：US11241141

申请日：2005-09-30

申请人： Norman J. Beamish ,  Morten Damgaard ,  John E. Vasa

发明人： Norman J. Beamish ,  Morten Damgaard ,  John E. Vasa

IPC分类号： H03M1/66

CPC分类号： H03M1/007 ,  H03M1/66

摘要： A system for reducing digital-to-analog converter (DAC) resolution for an amplitude modulated signal comprises a first logic configured to determine a desired DAC output voltage range, a second logic configured to select a DAC reference voltage level corresponding to the desired DAC output voltage range, a third logic configured to select a number of digital bits for conversion to the analog domain, the number of bits chosen from a larger number of digital bits, and a DAC configured to receive the selected DAC reference voltage level and convert the selected number of digital bits to a signal in the analog domain.

摘要翻译： 用于减小幅度调制信号的数模转换器（DAC）分辨率的系统包括被配置为确定期望的DAC输出电压范围的第一逻辑，被配置为选择对应于期望的DAC输出的DAC参考电压电平的第二逻辑 电压范围，第三逻辑，被配置为选择用于转换到模拟域的多个数字位，从较大数量位选择的位数，以及被配置为接收所选择的DAC参考电压电平并将所选择的DAC 数字位数到模拟域中的信号。

公开(公告)号：US08565358B2

公开(公告)日：2013-10-22

申请号：US13361247

申请日：2012-01-30

申请人： Jaleh Komaili ,  John E. Vasa ,  Thomas Obkircher

发明人： Jaleh Komaili ,  John E. Vasa ,  Thomas Obkircher

IPC分类号： H04B17/00

CPC分类号： H04L27/3809 ,  H03G3/3089 ,  H04L27/2647

摘要： A system provides closed-loop gain control in a WCDMA mode and open loop control in an EDGE/GSM mode. Gain control is distributed across analog devices and a digital scaler in a wireless receiver. In the WCDMA mode, a loop filter generates an error signal that is forwarded to analog and digital control paths. The analog control path includes a first adder, a programmable hysteresis element, and a lookup table. The analog control signal is responsive to thresholds, which when used in conjunction with a previous gain value determine a new gain value. The digital control path includes a second adder, a programmable delay element, and a converter. A control word is responsive to a difference of the error signal, a calibration value, and the analog control signal. Blocker detection is provided in the WCDMA mode of operation. A controller sets system parameters using a state machine.

公开(公告)号：US07231193B2

公开(公告)日：2007-06-12

申请号：US10822919

申请日：2004-04-13

申请人： Bala Ramachandran ,  John E. Vasa

发明人： Bala Ramachandran ,  John E. Vasa

IPC分类号： H04B1/00 ,  H04B1/10

CPC分类号： H03F1/30 ,  H03F2200/294 ,  H03F2200/331 ,  H03F2200/372 ,  H04B1/30

摘要： A system and method for direct current offset correction are disclosed. One embodiment of the system includes a direct current offset correction circuitry having an adjustable bandwidth and control logic configured to effect a bandwidth change of the direct current offset correction circuitry to speed up warm-up and settling time of the direct current offset correction circuitry.

摘要翻译： 公开了用于直流偏移校正的系统和方法。 该系统的一个实施例包括直流偏移校正电路，其具有可调节带宽和控制逻辑，其被配置为实现直流偏移校正电路的带宽变化，以加速直流偏移校正电路的预热和建立时间。

公开(公告)号：US07415264B2

公开(公告)日：2008-08-19

申请号：US10949534

申请日：2004-09-25

申请人： Aly Ismail ,  John E. Vasa ,  Balasubramanian Ramachandran

发明人： Aly Ismail ,  John E. Vasa ,  Balasubramanian Ramachandran

IPC分类号： H04B1/16 ,  H04B1/10

CPC分类号： H04B1/30 ,  H03F3/45968 ,  H03F2200/294 ,  H03F2200/372

摘要： A low noise filter is arranged to receive an input signal from a downconverter. The low noise filter is constructed to block or cancel any DC offset in the input signal, as well as filter selected frequency components from the input signal. The low noise filter uses a shared capacitor both to handle the DC offset and to set filter response characteristics. As the low noise filter is implemented with a Frequency Dependent Negative Resistance (FDNR) device, the shared capacitor may be relatively small. The low noise filter has a load capacitor, with the output of the load capacitor coupled to a bias resistor and voltage. This bias structure cooperates with the load capacitor to set a high cutoff frequency for the low noise filter useful for blocking or canceling the DC offset.

摘要翻译： 低噪声滤波器布置成从下变频器接收输入信号。 低噪声滤波器被构造为阻挡或消除输入信号中的任何DC偏移，以及从输入信号中滤除所选择的频率分量。 低噪声滤波器使用共享电容器来处理DC偏移并设置滤波器响应特性。 由于利用频率相关负电阻（FDNR）器件实现低噪声滤波器，所以共享电容器可能相对较小。 低噪声滤波器具有负载电容，负载电容的输出耦合到偏置电阻和电压。 该偏置结构与负载电容器配合，为低噪声滤波器设置高截止频率，可用于阻断或抵消DC偏移。

公开(公告)号：US20080232268A1

公开(公告)日：2008-09-25

申请号：US12052991

申请日：2008-03-21

申请人： Masoud Kahrizi ,  Jaleh Komaili ,  John E. Vasa

发明人： Masoud Kahrizi ,  Jaleh Komaili ,  John E. Vasa

IPC分类号： H04J1/16

CPC分类号： H04B1/525 ,  H04B1/30

摘要： A transmit signal second-order inter-modulation (IM2) canceller for a portable handset using a full duplex mode of operation (e.g., WCDMA) is used to controllably reduce IM2 introduced by a transmit signal that appears in a received signal in a receive channel of the portable handset. The transmit signal IM2 canceller includes a delay estimator and a digital signal adjuster. The delay estimator receives a first input from a receive channel and a second input from a transmit channel. The delay estimator generates an estimate of the IM2 that the transmit channel introduces in the receive channel. The digital signal adjuster removes the estimate of the IM2 before forwarding a modified receive channel signal to a baseband subsystem of the portable handset.

摘要翻译： 使用用于使用全双工操作模式（例如，WCDMA）的便携式手持机的发射信号二阶互调制（IM 2）消除器可控制地减少出现在接收信号中的发射信号引入的IM 2 接收便携式手机的通道。 发送信号IM 2消除器包括延迟估计器和数字信号调节器。 延迟估计器从接收信道接收第一输入，并从发送信道接收第二输入。 延迟估计器产生发送信道在接收信道中引入的IM 2的估计。 在将修改的接收信道信号转发到便携式手持机的基带子系统之前，数字信号调节器去除IM 2的估计。

公开(公告)号：US08855029B2

公开(公告)日：2014-10-07

申请号：US12947905

申请日：2010-11-17

申请人： Masoud Kahrizi ,  Jaleh Komaili ,  John E. Vasa

发明人： Masoud Kahrizi ,  Jaleh Komaili ,  John E. Vasa

IPC分类号： H04B1/44 ,  H04B1/30 ,  H04B1/04 ,  H04B1/52 ,  H04B7/212 ,  H04B1/38 ,  H04L5/16 ,  H03D1/04 ,  H04L25/03

CPC分类号： H04B1/0475 ,  H04B1/30 ,  H04B1/525 ,  H04L25/03878

摘要： A transmit signal second-order inter-modulation (IM2) canceller for a portable handset using a full duplex mode of operation (e.g., WCDMA) is used to controllably reduce IM2 introduced by a transmit signal that appears in a received signal in a receive channel of the portable handset. The transmit signal IM2 canceller includes a delay estimator and a digital signal adjuster. The delay estimator receives a first input from a receive channel and a second input from a transmit channel. The delay estimator generates an estimate of the IM2 that the transmit channel introduces in the receive channel. The digital signal adjuster removes the estimate of the IM2 before forwarding a modified receive channel signal to a baseband subsystem of the portable handset.

摘要翻译： 用于使用全双工操作模式（例如，WCDMA）的便携式手机的发射信号二阶互调制（IM2）消除器被用于可控制地减少出现在接收信道中的接收信号中的发射信号引入的IM2 的便携式手机。 发送信号IM2消除器包括延迟估计器和数字信号调节器。 延迟估计器从接收信道接收第一输入，并从发送信道接收第二输入。 延迟估计器产生发送信道在接收信道中引入的IM2的估计。 在将修改的接收信道信号转发到便携式手持机的基带子系统之前，数字信号调节器去除IM2的估计。

公开(公告)号：US08606311B2

公开(公告)日：2013-12-10

申请号：US12865687

申请日：2009-02-07

申请人： Yongqiang He ,  John E. Vasa ,  Masoud Kahrizi

发明人： Yongqiang He ,  John E. Vasa ,  Masoud Kahrizi

IPC分类号： H04B7/00

CPC分类号： H04W52/52 ,  H04W52/226 ,  H04W52/367

摘要： A mobile handset is arranged with an adaptive power controller to controllably adjust transmit power. The adaptive power controller is coupled to a power amplifier module to form a closed feedback loop. The adaptive power control module includes a first shifter, a first sealer, an accumulator and a hold element. The first shifter and first sealer receive respective bandwidth control signals and an error signal. The first shifter and first sealer generate a modified error signal that is forwarded to and filtered by the accumulator and the hold element to generate a power control signal. The power control signal, which is generated the radio frequency subsystem of the handset can quickly and accurately track rapid changes in transmit power.

摘要翻译： 移动手机配置有自适应功率控制器以可控地调节发射功率。 自适应功率控制器耦合到功率放大器模块以形成闭合反馈回路。 自适应功率控制模块包括第一变速器，第一闭合器，蓄能器和保持元件。 第一移位器和第一密封器接收相应的带宽控制信号和误差信号。 第一移位器和第一密封器产生经过累加器和保持元件转发和滤波的修正误差信号，以产生功率控制信号。 产生手机射频子系统的功率控制信号可以快速，准确地跟踪发射功率的快速变化。