利索-全球专利检索

  1. Login
  2. Sign Up

Search Results

47 records (took 0.027 seconds)

    Method for reducing leakage currents caused by misalignment of a contact structure by increasing an error tolerance of the contact patterning process
    3.
    发明授权
    Method for reducing leakage currents caused by misalignment of a contact structure by increasing an error tolerance of the contact patterning process 有权
    一种通过增加接触图案化过程的误差容差来减小由接触结构的未对准引起的漏电流的方法

    公开(公告)号：US07998823B2

    公开(公告)日：2011-08-16

    申请号：US11533793

    申请日：2006-09-21

    Applicant: Carsten Peters ,  Kai Frohberg ,  Ralf Richter

    Inventor： Carsten Peters ,  Kai Frohberg ,  Ralf Richter

    IPC: H01L21/336

    CPC classification number: H01L21/823481 ,  H01L21/76897 ,  H01L21/823475

    Abstract: By forming an additional doped region with increased junction depth at areas in which contact regions may connect to drain and source regions, any contact irregularities may be embedded into the additional doped region, thereby reducing the risk for leakage currents or short circuits between the drain and source region and the well region that may be conventionally caused by the contact irregularity. Moreover, additionally or alternatively, the surface topography of the semiconductor region and the adjacent isolation trench may be modified prior to the formation of metal silicide regions and contact plugs to enhance the lithography procedure for forming respective contact openings in an interlayer dielectric material. For this purpose, the isolation trench may be brought to an equal or higher level compared to the adjacent semiconductor region.

    Abstract translation: 通过在接触区域可以连接到漏极和源极区域的区域处形成具有增加的结深度的附加掺杂区域，可以将任何接触不规则物嵌入到附加掺杂区域中，从而降低漏极和漏极之间的漏电流或短路的风险 源极区域和通常由接触不规则引起的阱区域。 此外，附加地或替代地，可以在形成金属硅化物区域和接触插塞之前修改半导体区域和相邻隔离沟槽的表面形貌，以增强在层间电介质材料中形成相应接触开口的光刻过程。 为此，与相邻的半导体区域相比，隔离沟槽可以达到相同或更高的水平。

    Technique for compensating for a difference in deposition behavior in an interlayer dielectric material
    4.
    发明授权
    Technique for compensating for a difference in deposition behavior in an interlayer dielectric material 有权
    补偿层间电介质材料沉积行为差异的技术

    公开(公告)号：US07875514B2

    公开(公告)日：2011-01-25

    申请号：US12841313

    申请日：2010-07-22

    Applicant: Ralf Richter ,  Robert Seidel ,  Carsten Peters

    Inventor： Ralf Richter ,  Robert Seidel ,  Carsten Peters

    IPC: H01L21/8238

    CPC classification number: H01L21/823807 ,  H01L21/76816 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76832 ,  H01L29/7843

    Abstract: By selectively providing a buffer layer having an appropriate thickness, height differences occurring during the deposition of an SACVD silicon dioxide may be reduced during the formation of an interlayer dielectric stack of advanced semiconductor devices. The buffer material may be selectively provided after the deposition of contact etch stop layers of both types of internal stress or may be provided after the deposition of one type of dielectric material and may be used during the subsequent patterning of the other type of dielectric stop material as an efficient etch stop layer.

    Abstract translation: 通过选择性地提供具有适当厚度的缓冲层，在形成先进的半导体器件的层间电介质叠层的过程中，可以减少沉积SACVD二氧化硅期间出现的高度差异。 可以在沉积两种类型的内部应力的接触蚀刻停止层之后选择性地提供缓冲材料，或者可以在沉积一种类型的电介质材料之后提供缓冲材料，并且可以在随后的其它类型的电介质停止材料的图案化期间使用缓冲材料 作为有效的蚀刻停止层。

    INCREASED RELIABILITY FOR A CONTACT STRUCTURE TO CONNECT AN ACTIVE REGION WITH A POLYSILICON LINE
    6.
    发明申请
    INCREASED RELIABILITY FOR A CONTACT STRUCTURE TO CONNECT AN ACTIVE REGION WITH A POLYSILICON LINE 有权
    连接活动区域与多晶硅线的接触结构的可靠性提高

    公开(公告)号：US20090085030A1

    公开(公告)日：2009-04-02

    申请号：US12056362

    申请日：2008-03-27

    Applicant: Carsten Peters ,  Ralf Richter ,  Kai Frohberg

    Inventor： Carsten Peters ,  Ralf Richter ,  Kai Frohberg

    IPC: H01L29/06 ,  H01L21/44 ,  H01L29/78

    CPC classification number: H01L23/485 ,  H01L21/28518 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: By forming a direct contact structure connecting, for instance, a polysilicon line with an active region on the basis of an increased amount of metal silicide by removing the sidewall spacers prior to the silicidation process, a significantly increased etch selectivity may be achieved during the contact etch stop layer opening. Hence, undue etching of the highly doped silicon material of the active region would be suppressed. Additionally or alternatively, an appropriately designed test structure is disclosed, which may enable the detection of electrical characteristics of contact structures formed in accordance with a specified manufacturing sequence and on the basis of specific design criteria.

    Abstract translation: 通过形成直接接触结构，例如通过在硅化处理之前去除侧壁间隔物，在增加量的金属硅化物的基础上连接有源区域，可以在接触期间实现显着增加的蚀刻选择性 蚀刻停止层开口。 因此，有效区域的高掺杂硅材料的过度蚀刻将被抑制。 附加地或替代地，公开了适当设计的测试结构，其可以检测根据特定制造顺序形成的接触结构的电特性，并且可以基于特定的设计标准。

    TECHNIQUE FOR NON-DESTRUCTIVE METAL DELAMINATION MONITORING IN SEMICONDUCTOR DEVICES
    7.
    发明申请
    TECHNIQUE FOR NON-DESTRUCTIVE METAL DELAMINATION MONITORING IN SEMICONDUCTOR DEVICES 有权
    半导体器件非破坏性金属分层监测技术

    公开(公告)号：US20070178691A1

    公开(公告)日：2007-08-02

    申请号：US11536730

    申请日：2006-09-29

    Applicant: Ralf Richter ,  Carsten Peters ,  Holger Schuehrer

    Inventor： Ralf Richter ,  Carsten Peters ,  Holger Schuehrer

    IPC: H01L21/4763

    CPC classification number: H01L23/544 ,  H01L21/7684 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: By providing large area metal plates in combination with respective peripheral areas of increased adhesion characteristics, delamination events may be effectively monitored substantially without negatively affecting the overall performance of the semiconductor device during processing and operation. In some illustrative embodiments, dummy vias may be provided at the periphery of a large area metal plate, thereby allowing delamination in the central area while substantially avoiding a complete delamination of the metal plate. Consequently, valuable information with respect to mechanical characteristics of the metallization layer as well as process flow parameters may be efficiently monitored.

    Abstract translation: 通过提供大面积金属板与相应的周边区域结合增加的粘合特性，可以有效地监测分层事件，而不会在加工和操作过程中不影响半导体器件的整体性能。 在一些示例性实施例中，可以在大面积金属板的周边设置虚拟通孔，从而允许中心区域分层，同时基本避免金属板的完全分层。 因此，可以有效地监测关于金属化层的机械特性以及工艺流程参数的有价值的信息。

    METHOD FOR REDUCING LEAKAGE CURRENTS CAUSED BY MISALIGNMENT OF A CONTACT STRUCTURE BY INCREASING AN ERROR TOLERANCE OF THE CONTACT PATTERNING PROCESS
    9.
    发明申请
    METHOD FOR REDUCING LEAKAGE CURRENTS CAUSED BY MISALIGNMENT OF A CONTACT STRUCTURE BY INCREASING AN ERROR TOLERANCE OF THE CONTACT PATTERNING PROCESS 有权
    通过增加联系方式的错误容忍来减少接触结构的误差造成的泄漏电流的方法

    公开(公告)号：US20070161225A1

    公开(公告)日：2007-07-12

    申请号：US11533793

    申请日：2006-09-21

    Applicant: Carsten Peters ,  Kai Frohberg ,  Ralf Richter

    Inventor： Carsten Peters ,  Kai Frohberg ,  Ralf Richter

    IPC: H01L21/76 ,  H01L21/4763 ,  H01L21/44

    CPC classification number: H01L21/823481 ,  H01L21/76897 ,  H01L21/823475

    Abstract: By forming an additional doped region with increased junction depth at areas in which contact regions may connect to drain and source regions, any contact irregularities may be embedded into the additional doped region, thereby reducing the risk for leakage currents or short circuits between the drain and source region and the well region that may be conventionally caused by the contact irregularity. Moreover, additionally or alternatively, the surface topography of the semiconductor region and the adjacent isolation trench may be modified prior to the formation of metal silicide regions and contact plugs to enhance the lithography procedure for forming respective contact openings in an interlayer dielectric material. For this purpose, the isolation trench may be brought to an equal or higher level compared to the adjacent semiconductor region.

    Abstract translation: 通过在接触区域可以连接到漏极和源极区域的区域处形成具有增加的结深度的附加掺杂区域，可以将任何接触不规则物嵌入到附加掺杂区域中，从而降低漏极和漏极之间的漏电流或短路的风险 源极区域和通常由接触不规则引起的阱区域。 此外，附加地或替代地，可以在形成金属硅化物区域和接触插塞之前修改半导体区域和相邻隔离沟槽的表面形貌，以增强在层间电介质材料中形成相应接触开口的光刻过程。 为此，与相邻的半导体区域相比，隔离沟槽可以达到相同或更高的水平。

    TECHNIQUE FOR COMPENSATING FOR A DIFFERENCE IN DEPOSITION BEHAVIOR IN AN INTERLAYER DIELECTRIC MATERIAL
    10.
    发明申请
    TECHNIQUE FOR COMPENSATING FOR A DIFFERENCE IN DEPOSITION BEHAVIOR IN AN INTERLAYER DIELECTRIC MATERIAL 有权
    用于补偿中间层介质材料中沉积行为差异的技术

    公开(公告)号：US20100285668A1

    公开(公告)日：2010-11-11

    申请号：US12841313

    申请日：2010-07-22

    Applicant: Ralf Richter ,  Robert Seidel ,  Carsten Peters

    Inventor： Ralf Richter ,  Robert Seidel ,  Carsten Peters

    IPC: H01L21/311 ,  H01L21/31

    CPC classification number: H01L21/823807 ,  H01L21/76816 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76832 ,  H01L29/7843

    Abstract: By selectively providing a buffer layer having an appropriate thickness, height differences occurring during the deposition of an SACVD silicon dioxide may be reduced during the formation of an interlayer dielectric stack of advanced semiconductor devices. The buffer material may be selectively provided after the deposition of contact etch stop layers of both types of internal stress or may be provided after the deposition of one type of dielectric material and may be used during the subsequent patterning of the other type of dielectric stop material as an efficient etch stop layer.

    Abstract translation: 通过选择性地提供具有适当厚度的缓冲层，在形成先进的半导体器件的层间电介质叠层的过程中，可以减少沉积SACVD二氧化硅期间出现的高度差异。 可以在沉积两种类型的内部应力的接触蚀刻停止层之后选择性地提供缓冲材料，或者可以在沉积一种类型的电介质材料之后提供缓冲材料，并且可以在随后的其它类型的电介质停止材料的图案化期间使用缓冲材料 作为有效的蚀刻停止层。

Patent Agency Ranking