公开(公告)号：US09417800B2

公开(公告)日：2016-08-16

申请号：US14965845

申请日：2015-12-10

Applicant: Rambus Inc.

Inventor： Billy Garrett, Jr.

IPC: G06F12/00 ,  G06F3/06 ,  G11C7/10

CPC classification number: G06F3/0613 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0629 ,  G06F3/0659 ,  G06F3/0665 ,  G06F3/0673 ,  G06F3/0689 ,  G11C7/1042 ,  G11C7/1072

Abstract: A memory is disclosed comprising a first memory portion, a second memory portion, and an interface, wherein the memory portions are electrically isolated from each other and the interface is capable of receiving a row command and a column command in the time it takes to cycle the memory once. By interleaving access requests (comprising row commands and column commands) to the different portions of the memory, and by properly timing these access requests, it is possible to achieve full data bus utilization in the memory without increasing data granularity.

公开(公告)号：US10146445B2

公开(公告)日：2018-12-04

申请号：US15209429

申请日：2016-07-13

Applicant: Rambus Inc.

Inventor： Billy Garrett, Jr.

IPC: G06F12/00 ,  G06F3/06 ,  G11C7/10

Abstract: A memory is disclosed comprising a first memory portion, a second memory portion, and an interface, wherein the memory portions are electrically isolated from each other and the interface is capable of receiving a row command and a column command in the time it takes to cycle the memory once. By interleaving access requests (comprising row commands and column commands) to the different portions of the memory, and by properly timing these access requests, it is possible to achieve full data bus utilization in the memory without increasing data granularity.

公开(公告)号：US10860216B2

公开(公告)日：2020-12-08

申请号：US16177199

申请日：2018-10-31

Applicant: Rambus Inc.

Inventor： Billy Garrett, Jr.

IPC: G06F3/06 ,  G11C7/10

Abstract: A memory is disclosed comprising a first memory portion, a second memory portion, and an interface, wherein the memory portions are electrically isolated from each other and the interface is capable of receiving a row command and a column command in the time it takes to cycle the memory once. By interleaving access requests (comprising row commands and column commands) to the different portions of the memory, and by properly timing these access requests, it is possible to achieve full data bus utilization in the memory without increasing data granularity.

公开(公告)号：US09257161B2

公开(公告)日：2016-02-09

申请号：US14476334

申请日：2014-09-03

Applicant: Rambus Inc.

Inventor： Billy Garrett, Jr.

IPC: G06F12/00 ,  G11C7/10 ,  G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0629 ,  G06F3/0659 ,  G06F3/0665 ,  G06F3/0673 ,  G06F3/0689 ,  G11C7/1042 ,  G11C7/1072

Abstract: A memory is disclosed comprising a first memory portion, a second memory portion, and an interface, wherein the memory portions are electrically isolated from each other and the interface is capable of receiving a row command and a column command in the time it takes to cycle the memory once. By interleaving access requests (comprising row commands and column commands) to the different portions of the memory, and by properly timing these access requests, it is possible to achieve full data bus utilization in the memory without increasing data granularity.

公开(公告)号：US08856480B2

公开(公告)日：2014-10-07

申请号：US13720585

申请日：2012-12-19

Applicant: Rambus Inc.

Inventor： Billy Garrett, Jr.

IPC: G06F12/00 ,  G11C7/10

CPC classification number: G06F3/0613 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0629 ,  G06F3/0659 ,  G06F3/0665 ,  G06F3/0673 ,  G06F3/0689 ,  G11C7/1042 ,  G11C7/1072

Abstract: A memory is disclosed comprising a first memory portion, a second memory portion, and an interface, wherein the memory portions are electrically isolated from each other and the interface is capable of receiving a row command and a column command in the time it takes to cycle the memory once. By interleaving access requests (comprising row commands and column commands) to the different portions of the memory, and by properly timing these access requests, it is possible to achieve full data bus utilization in the memory without increasing data granularity.

Abstract translation: 公开了一种存储器，其包括第一存储器部分，第二存储器部分和接口，其中存储器部分彼此电隔离，并且接口能够在循环所需的时间内接收行命令和列命令 一次记忆 通过将访问请求（包括行命令和列命令）交织到存储器的不同部分，并且通过适当定时这些访问请求，可以在不增加数据粒度的情况下在存储器中实现完整的数据总线利用。