公开(公告)号：US20240283677A1

公开(公告)日：2024-08-22

申请号：US18590039

申请日：2024-02-28

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  Abhijit Abhyankar

IPC: H04L25/03 ,  G06F3/05 ,  G06F3/06 ,  G11C19/00

CPC classification number: H04L25/03057 ,  G06F3/05 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0673 ,  G11C19/00 ,  H04L25/03146 ,  H04L25/03878

Abstract: A first sequence of data bits is shifted into storage elements of a signal receiver during a first sequence of bit-time intervals, and a memory access command indicates that a second sequence of data bits is to be received within the signal receiver during a second sequence of bit-time intervals. Contents of the shift-register storage elements are conditionally overwritten with a predetermined set of seed bits, depending on whether one or more bit-time intervals will transpire between the first and second sequences of bit-time intervals. Equalization signals generated based, at least in part, on contents of the shift-register storage elements are used to adjust respective signal levels representative of one or more bits of the second sequence of data bits.

公开(公告)号：US11949539B2

公开(公告)日：2024-04-02

申请号：US17516502

申请日：2021-11-01

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  Abhijit Abhyankar

IPC: H04L25/03 ,  G06F3/05 ,  G06F3/06 ,  G11C19/00

CPC classification number: H04L25/03057 ,  G06F3/05 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0673 ,  G11C19/00 ,  H04L25/03146 ,  H04L25/03878

Abstract: A first sequence of data bits is shifted into storage elements of a signal receiver during a first sequence of bit-time intervals, and a memory access command indicates that a second sequence of data bits is to be received within the signal receiver during a second sequence of bit-time intervals. Contents of the shift-register storage elements are conditionally overwritten with a predetermined set of seed bits, depending on whether one or more bit-time intervals will transpire between the first and second sequences of bit-time intervals. Equalization signals generated based, at least in part, on contents of the shift-register storage elements are used to adjust respective signal levels representative of one or more bits of the second sequence of data bits.

公开(公告)号：US11573849B2

公开(公告)日：2023-02-07

申请号：US17236445

申请日：2021-04-21

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  Catherine Chen ,  Scott C. Best ,  John Eric Linstadt ,  Frederick A. Ware

IPC: G06F11/07 ,  G11C29/44 ,  G06F13/00 ,  G11C5/04 ,  G11C7/20 ,  G11C8/12 ,  G11C29/26

Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.

公开(公告)号：US20220366960A1

公开(公告)日：2022-11-17

申请号：US17852286

申请日：2022-06-28

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

IPC: G11C11/4076 ,  G06F3/06 ,  G06F5/06 ,  G06F1/08 ,  G11C7/10 ,  G11C29/02 ,  G06F13/16 ,  G06F12/06 ,  G11C11/409

Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

公开(公告)号：US20220350763A1

公开(公告)日：2022-11-03

申请号：US17748762

申请日：2022-05-19

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern ,  John Eric Linstadt ,  Thomas J. Giovannini ,  Kenneth L. Wright

IPC: G06F13/28 ,  G11C5/04 ,  G11C7/10 ,  G06F13/16

Abstract: The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.

公开(公告)号：US11211114B2

公开(公告)日：2021-12-28

申请号：US16503189

申请日：2019-07-03

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  John E. Linstadt ,  Thomas J. Giovannini ,  Scott C. Best ,  Kenneth L. Wright

IPC: G11C5/02 ,  G11C11/4093 ,  G11C5/06 ,  G11C11/4076 ,  G11C11/408 ,  G11C29/00 ,  H01L25/065 ,  H01L25/10 ,  G11C11/4096 ,  H01L25/18 ,  G11C7/10 ,  G11C8/12 ,  H01L23/00

Abstract: A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. Each DRAM component includes multiplexers that allow either of the data interfaces to write data to or read data from a common set of memory banks, and to selectively relay write and read data to and from other components, bypassing the local banks. Delay elements can impose selected read/write delays to align read and write transactions from and to disparate DRAM components.

公开(公告)号：US11184197B2

公开(公告)日：2021-11-23

申请号：US16418358

申请日：2019-05-21

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  Abhijit Abhyankar

IPC: H04L25/03 ,  G06F3/05 ,  G06F3/06 ,  G11C19/00

Abstract: A first sequence of data bits is shifted into storage elements of a signal receiver during a first sequence of bit-time intervals, and a memory access command indicates that a second sequence of data bits is to be received within the signal receiver during a second sequence of bit-time intervals. Contents of the shift-register storage elements are conditionally overwritten with a predetermined set of seed bits, depending on whether one or more bit-time intervals will transpire between the first and second sequences of bit-time intervals. Equalization signals generated based, at least in part, on contents of the shift-register storage elements are used to adjust respective signal levels representative of one or more bits of the second sequence of data bits.

公开(公告)号：US10331587B2

公开(公告)日：2019-06-25

申请号：US15498065

申请日：2017-04-26

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Thomas J. Giovannini

IPC: G06F12/00 ,  G06F13/16 ,  G11C7/10 ,  G11C7/22

Abstract: Apparatus and methods for operation of a memory controller, memory device and system are described. During operation, the memory controller transmits a read command which specifies that a memory device output data accessed from a memory core. This read command contains information which specifies whether the memory device is to commence outputting of a timing reference signal prior to commencing outputting of the data. The memory controller receives the timing reference signal if the information specified that the memory device output the timing reference signal. The memory controller subsequently samples the data output from the memory device based on information provided by the timing reference signal output from the memory device.

公开(公告)号：US20170351627A1

公开(公告)日：2017-12-07

申请号：US15533630

申请日：2015-10-28

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern ,  John Eric Linstadt ,  Thomas J. Giovannini ,  Kenneth L. Wright

IPC: G06F13/28 ,  G06F13/16

CPC classification number: G06F13/287 ,  G06F13/16 ,  G06F2213/28 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1045

Abstract: The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.

公开(公告)号：US09552865B2

公开(公告)日：2017-01-24

申请号：US14931513

申请日：2015-11-03

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

IPC: G11C11/4076 ,  G06F3/06 ,  G06F5/06 ,  G06F1/08 ,  G11C7/10 ,  G06F13/16 ,  G06F12/06 ,  G11C11/409 ,  G11C11/4096

CPC classification number: G11C11/4076 ,  G06F1/08 ,  G06F3/0629 ,  G06F3/0634 ,  G06F5/06 ,  G06F12/0646 ,  G06F13/1689 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C11/409 ,  G11C11/4096 ,  G11C2207/2254

Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

Abstract translation: 描述了校准执行写操作所涉及的信号之间的时序关系的系统。 该系统包括耦合到一组存储器芯片的存储器控​​制器，其中每个存储器芯片包括相位检测器，该相位检测器被配置为在数据选通信号和存储器芯片之间从存储器控制器接收的时钟信号之间校准相位关系 一个写操作。 此外，存储器控制器被配置为执行一个或多个写入读取验证操作以校准数据选通信号和时钟信号之间的时钟周期关系，其中写入 - 读取验证操作涉及改变在 相对于时钟信号的数据选通信号乘以时钟周期的倍数。