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21 条记录 (耗时 0.031 秒)

    Method for in-situ environment sensitive sealing and/or product controlling
    4.
    发明授权
    Method for in-situ environment sensitive sealing and/or product controlling 失效
    用于原位环境敏感密封和/或产品控制的方法

    公开(公告)号：US5628849A

    公开(公告)日：1997-05-13

    申请号：US451933

    申请日：1995-05-26

    申请人： Benjamin V. Fasano ,  Johnathan S. Fish ,  Gregory M. Johnson ,  Subhash L. Shinde

    发明人： Benjamin V. Fasano ,  Johnathan S. Fish ,  Gregory M. Johnson ,  Subhash L. Shinde

    IPC分类号： C04B35/638 ,  B22F3/10 ,  F27D1/18 ,  F27D5/00 ,  B32B9/00 ,  C03B29/00 ,  C04B33/34

    CPC分类号： F27D5/0068 ,  F27D5/0037 ,  F27D99/0073 ,  F27D1/18

    摘要： A single furnace loading cycle technique and a ventable sintering box therefor are disclosed for the sintering of products, such as, ceramic substrates. The sintering box includes a closeable cover which is held open by collapsible or deformable or sensitive spacers in a first furnace temperature range. The sensitive spacers collapse or deform in a higher temperature range to seal closed the box and the substrates therein. Additional spacers may be used for applying weight upon the substrates at the higher temperature range. Thus, volatile agents within the substrates are permitted to escape in the first temperature range but are prevented from escaping in the higher temperature range and in situ sintering weights can be applied without removing the substrates from the furnace.

    摘要翻译： 公开了一种单炉加载循环技术及其可通气烧结盒，用于陶瓷衬底等产品的烧结。 烧结箱包括在第一炉温度范围内由可折叠或可变形或敏感的隔离物保持打开的可关闭盖。 敏感间隔件在更高的温度范围内崩溃或变形，以密封箱体和其中的基板。 可以使用附加的间隔物来在较高温度范围的基底上施加重量。 因此，允许基板内的挥发性物质在第一温度范围内逸出，但是在较高温度范围内可防止其逸出，并且可以施加原位烧结重量而不从炉中移走基板。

    VIA CHAINS FOR DEFECT LOCALIZATION
    8.
    发明申请
    VIA CHAINS FOR DEFECT LOCALIZATION 失效
    通过缺陷定位的链条

    公开(公告)号：US20130082257A1

    公开(公告)日：2013-04-04

    申请号：US13251352

    申请日：2011-10-03

    申请人： Bahierathan Balasingham ,  Christopher B. D'Aleo ,  Gregory M. Johnson ,  Muthukumarasamy Karthikeyan ,  Shenzhi Yang

    发明人： Bahierathan Balasingham ,  Christopher B. D'Aleo ,  Gregory M. Johnson ,  Muthukumarasamy Karthikeyan ,  Shenzhi Yang

    IPC分类号： H01L23/48 ,  H01L21/66

    CPC分类号： H01L22/30 ,  H01L22/14 ,  H01L22/20 ,  H01L22/34

    摘要： Method form via chain and serpentine/comb test structures in kerf areas of a wafer. The via chain test structures comprise a first via chain and a second via chain in a first kerf area. The via chain test structures are formed such that geometrically shaped portions of the first via chain and geometrically shaped portions of the second via chain alternate along the length of the first kerf area. The methods perform relatively low (first) magnification testing to identify a defective geometrically shaped portion that contains a defective via structure. The methods then perform relatively high (second) magnification testing only within the defective geometrically shaped portion. The first magnification testing is performed at a lower magnification relative to the second magnification testing.

    摘要翻译： 通过链条和蛇纹石/梳状测试结构在晶片的切口区域中的方法形式。 通孔链测试结构包括在第一切口区域中的第一通孔链和第二通孔链。 通孔链测试结构被形成为使得第一通孔链的几何形状部分和第二通孔链的几何形状部分沿着第一切口区域的长度交替。 该方法执行相对较低（第一）倍率测试以识别包含有缺陷的通孔结构的有缺陷的几何形状的部分。 然后，该方法仅在缺陷几何形状部分内执行相对高（第二）放大率测试。 相对于第二倍率测试，以较低的放大倍数执行第一放大率测试。

    Thermoelectric devices and methods for making the same
    9.
    发明授权
    Thermoelectric devices and methods for making the same 失效
    热电器件及其制造方法

    公开(公告)号：US06262357B1

    公开(公告)日：2001-07-17

    申请号：US09543269

    申请日：2000-04-05

    申请人： Gregory M. Johnson ,  Jon A. Casey ,  Scott R. Dwyer ,  David C. Long ,  Kevin M. Prettyman

    发明人： Gregory M. Johnson ,  Jon A. Casey ,  Scott R. Dwyer ,  David C. Long ,  Kevin M. Prettyman

    IPC分类号： H01L3528

    CPC分类号： H01L23/38 ,  H01L35/32 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2224/0401

    摘要： Thermoelectric devices having enhanced thermal characteristics are fabricated using multilayer ceramic (MLC) technology methods. Aluminum nitride faceplates with embedded electrical connections provide the electrical series configuration for alternating dissimilar semiconducting materials. Embedded electrical connections are formed by vias and lines in the faceplate. Methods for forming tunnels through lamination and etching are employed. A portion of the dissimilar materials are then melted within the tunnels to form a bond. Thermal conductivity of the faceplate is enhanced by adding electrically isolated vias to one surface, filled with high thermal conductivity metal paste. A low thermal conductivity material is also introduced between the two high thermal conductivity material faceplates. Alternating semiconducting materials are introduced within the varying thermal conductivity layers by punching vias within greensheets of predetermined thermal conductivity and filling with n-type and p-type paste. Alternating semiconducting materials may also be patterned in linear or radial fanout patterns through screening techniques and lamination of wire structures. A liquid channel within the faceplate is used to enhance thermal energy transfer. Thermoelectric devices are physically incorporated within the IC package using MLC technology.

    摘要翻译： 具有增强的热特性的热电装置使用多层陶瓷（MLC）技术方法制造。 具有嵌入式电连接的氮化铝面板为交替的不同的半导体材料提供了电气串联配置。 嵌入式电气连接由面板中的通孔和线形成。 采用通过层压和蚀刻形成隧道的方法。 然后将不同材料的一部分在隧道内熔化以形成粘结。 通过向一个表面添加电隔离的通孔，填充高导热性金属膏，增强了面板的导热性。 在两个高导热材料面板之间还引入低导热材料。通过在预定导热率的孔内冲压通孔并填充n型和p型浆料，将不同的导热层引入异构半导体材料。 交替的半导体材料还可以通过屏蔽技术和线结构的层叠来以线性或径向扇出图案图案化。 面板内的液体通道用于增强热能传递。热电器件使用MLC技术物理地并入IC封装内。

    Method and apparatus for removing known good die
    10.
    发明授权
    Method and apparatus for removing known good die 失效
    去除已知好模具的方法和装置

    公开(公告)号：US06360940B1

    公开(公告)日：2002-03-26

    申请号：US09709092

    申请日：2000-11-08

    申请人： Lannie R. Bolde ,  James Hennekens ,  Gregory M. Johnson ,  David Olson

    发明人： Lannie R. Bolde ,  James Hennekens ,  Gregory M. Johnson ,  David Olson

    IPC分类号： B23K1018

    CPC分类号： H01L21/67144 ,  B23K1/018 ,  H01L21/67253

    摘要： Preferred embodiments for methods of removing an integrated circuit (“IC”) from a substrate, where the IC is attached to the substrate by multiple solder connections are disclosed. One preferred embodiment of the inventive methods provides the steps of heating the IC and substrate to the reflow temperature for the solder connections and pulling the IC from the substrate by means of a vacuum force. Another preferred embodiment of the inventive method provides the step of shearing the IC from the substrate after the substrate and IC are heated, but before solder reflow temperature has been reached, and where the shearing force may be programmed through a computer controlled servomotor. Preferred embodiments of certain apparatus applying the inventive methods for removing an integrated circuit from a substrate are also disclosed. One preferred embodiment of the inventive apparatus includes a vented pallet to hold the substrate and IC and through which the vacuum force is applied to pull the IC from the substrate without the use of physical clamping or contact forces applied to the substrate or IC. In a further preferred embodiment of the inventive apparatus, shear elements are provided and used with a programmable servomotor for precisely controlling the forces applied to the substrate and IC as a function of time, temperature and translational distance.

    摘要翻译： 公开了用于通过多个焊接连接将集成电路附接到衬底的衬底去除集成电路（“IC”）的方法的优选实施例。 本发明方法的一个优选实施例提供了将IC和衬底加热至用于焊料连接的回流温度并通过真空力将IC从衬底拉出的步骤。 本发明方法的另一优选实施例提供了在衬底和IC被加热之后但在达到焊锡回流温度之前以及剪切力可以通过计算机控制的伺服电动机编程的情况下从衬底剪切IC的步骤。 还公开了应用本发明的从基板去除集成电路的方法的某些设备的优选实施例。 本发明装置的一个优选实施例包括一个通风的托盘，用于保持基板和IC，并且通过其施加真空力以将IC从基板拉出，而不用施加到基板或IC上的物理夹紧或接触力。 在本发明装置的另一优选实施例中，提供剪切元件并与可编程伺服电机一起使用，用于根据时间，温度和平移距离精确控制施加到基板和IC的力。