公开(公告)号：US08446006B2

公开(公告)日：2013-05-21

申请号：US12640752

申请日：2009-12-17

申请人： Raschid J. Bezama ,  Timothy H. Daubenspeck ,  Gary LaFontant ,  Ian D. Melville ,  Ekta Misra ,  George J. Scott ,  Krystyna W. Semkow ,  Timothy D. Sullivan ,  Robin A. Susko ,  Thomas A. Wassick ,  Xiaojin Wei ,  Steven L. Wright

发明人： Raschid J. Bezama ,  Timothy H. Daubenspeck ,  Gary LaFontant ,  Ian D. Melville ,  Ekta Misra ,  George J. Scott ,  Krystyna W. Semkow ,  Timothy D. Sullivan ,  Robin A. Susko ,  Thomas A. Wassick ,  Xiaojin Wei ,  Steven L. Wright

IPC分类号： H01L23/498 ,  H01L21/3205

CPC分类号： H01L23/49816 ,  H01L21/76804 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05013 ,  H01L2224/05094 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

摘要： Structures and methods to reduce maximum current density in a solder ball are disclosed. A method includes forming a contact pad in a last wiring level and forming a plurality of wires of the contact pad extending from side edges of the contact pad to respective ones of a plurality of vias. Each one of the plurality of wires has substantially the same electrical resistance.

摘要翻译： 公开了减少焊球中的最大电流密度的结构和方法。 一种方法包括在最后的布线层中形成接触焊盘，并且形成从接触焊盘的侧边缘延伸到多个通孔中的多个通孔的接触焊盘的多个导线。 多个导线中的每一根具有基本上相同的电阻。

公开(公告)号：US08487447B2

公开(公告)日：2013-07-16

申请号：US13111283

申请日：2011-05-19

申请人： Mario J. Interrante ,  Gary LaFontant ,  Michael J. Shapiro ,  Thomas A. Wassick ,  Bucknell C. Webb

发明人： Mario J. Interrante ,  Gary LaFontant ,  Michael J. Shapiro ,  Thomas A. Wassick ,  Bucknell C. Webb

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/3171 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02163 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05551 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/0569 ,  H01L2224/06131 ,  H01L2224/06134 ,  H01L2224/13005 ,  H01L2224/13016 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13026 ,  H01L2224/13028 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/049 ,  H01L2924/053 ,  H01L2224/05552

摘要： A semiconductor structure which includes a plurality of stacked semiconductor chips in a three dimensional configuration. There is a first semiconductor chip in contact with a second semiconductor chip. The first semiconductor chip includes a through silicon via (TSV) extending through the first semiconductor chip; an electrically conducting pad at a surface of the first semiconductor chip, the TSV terminating in contact at a first side of the electrically conducting pad; a passivation layer covering the electrically conducting pad, the passivation layer having a plurality of openings; and a plurality of electrically conducting structures formed in the plurality of openings and in contact with a second side of the electrically conducting pad, the contact of the plurality of electrically conducting structures with the electrically conducting pad being offset with respect to the contact of the TSV with the electrically conducting pad.

摘要翻译： 一种半导体结构，其包括三维结构中的多个层叠半导体芯片。 存在与第二半导体芯片接触的第一半导体芯片。 第一半导体芯片包括延伸穿过第一半导体芯片的贯穿硅通孔（TSV）; 在所述第一半导体芯片的表面处的导电焊盘，所述TSV终止于所述导电焊盘的第一侧接触; 覆盖所述导电焊盘的钝化层，所述钝化层具有多个开口; 以及形成在所述多个开口中并与所述导电垫的第二侧接触的多个导电结构，所述多个导电结构与所述导电垫的接触相对于所述TSV的接触而偏移 与导电垫。

公开(公告)号：US20120292779A1

公开(公告)日：2012-11-22

申请号：US13111283

申请日：2011-05-19

申请人： MARIO J. INTERRANTE ,  Gary LaFontant ,  Michael J. Shapiro ,  Thomas A. Wassick ,  Bucknell C. Webb

发明人： MARIO J. INTERRANTE ,  Gary LaFontant ,  Michael J. Shapiro ,  Thomas A. Wassick ,  Bucknell C. Webb

IPC分类号： H01L23/48 ,  H01L21/28

CPC分类号： H01L23/3171 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02163 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05551 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/0569 ,  H01L2224/06131 ,  H01L2224/06134 ,  H01L2224/13005 ,  H01L2224/13016 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13026 ,  H01L2224/13028 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/049 ,  H01L2924/053 ,  H01L2224/05552

摘要： A semiconductor structure which includes a plurality of stacked semiconductor chips in a three dimensional configuration. There is a first semiconductor chip in contact with a second semiconductor chip. The first semiconductor chip includes a through silicon via (TSV) extending through the first semiconductor chip; an electrically conducting pad at a surface of the first semiconductor chip, the TSV terminating in contact at a first side of the electrically conducting pad; a passivation layer covering the electrically conducting pad, the passivation layer having a plurality of openings; and a plurality of electrically conducting structures formed in the plurality of openings and in contact with a second side of the electrically conducting pad, the contact of the plurality of electrically conducting structures with the electrically conducting pad being offset with respect to the contact of the TSV with the electrically conducting pad.

摘要翻译： 一种半导体结构，其包括三维结构中的多个层叠半导体芯片。 存在与第二半导体芯片接触的第一半导体芯片。 第一半导体芯片包括延伸穿过第一半导体芯片的贯穿硅通孔（TSV）; 在所述第一半导体芯片的表面处的导电焊盘，所述TSV终止于所述导电焊盘的第一侧接触; 覆盖所述导电焊盘的钝化层，所述钝化层具有多个开口; 以及形成在所述多个开口中并与所述导电垫的第二侧接触的多个导电结构，所述多个导电结构与所述导电垫的接触相对于所述TSV的接触而偏移 与导电垫。

公开(公告)号：US08237288B1

公开(公告)日：2012-08-07

申请号：US13023743

申请日：2011-02-09

申请人： Mukta G Farooq ,  John A Griesemer ,  Gary LaFontant ,  William Francis Landers ,  Timothy Dooling Sullivan

发明人： Mukta G Farooq ,  John A Griesemer ,  Gary LaFontant ,  William Francis Landers ,  Timothy Dooling Sullivan

IPC分类号： H01L23/48

CPC分类号： H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： The embodiments provide a method for reducing electromigration in a circuit containing a through-silicon via (TSV) and the resulting novel structure for the TSV. A TSV is formed through a semiconductor substrate. A first end of the TSV connects to a first metallization layer on a device side of the semiconductor substrate. A second end of the TSV connects to a second metallization layer on a grind side of the semiconductor substrate. A first flat edge is created on the first end of the TSV at the intersection of the first end of the TSV and the first metallization layer. A second flat edge is created on the second end of the TSV at the intersection of the second end of the TSV and the second metallization layer. On top of the first end a metal contact grid is placed, having less than eighty percent metal coverage.

公开(公告)号：US07271681B2

公开(公告)日：2007-09-18

申请号：US11160785

申请日：2005-07-08

申请人： Warren D. Dyckman ,  Gary LaFontant ,  Edward R. Pillai

发明人： Warren D. Dyckman ,  Gary LaFontant ,  Edward R. Pillai

IPC分类号： H03H7/38

CPC分类号： H05K1/115 ,  G06F17/5036 ,  G06F17/5068 ,  H05K1/0237 ,  H05K1/116 ,  H05K3/0005 ,  H05K2201/09236 ,  H05K2201/09718

摘要： The present invention provides a technique for adjusting the size of clearance holes for impedance control in multilayer electronic packaging and printed circuit boards. The method comprises: providing parameters for a structure having a clearance hole and at least one via passing through the clearance hole; calculating a characteristic impedance for the at least one via; and adjusting at least a size of the clearance hole until the characteristic impedance for the at least one via is approximately equal to a desired characteristic impedance.

摘要翻译： 本发明提供一种用于调整多层电子封装和印刷电路板中用于阻抗控制的间隙孔尺寸的技术。 该方法包括：为具有间隙孔和穿过间隙孔的至少一个通孔的结构提供参数; 计算所述至少一个通孔的特征阻抗; 以及至少调节所述间隙孔的尺寸，直到所述至少一个通孔的特征阻抗近似等于期望的特性阻抗。

公开(公告)号：US08288270B2

公开(公告)日：2012-10-16

申请号：US13397004

申请日：2012-02-15

申请人： Mukta G Farooq ,  John A Griesemer ,  Gary LaFontant ,  William Francis Landers ,  Timothy Dooling Sullivan

发明人： Mukta G Farooq ,  John A Griesemer ,  Gary LaFontant ,  William Francis Landers ,  Timothy Dooling Sullivan

IPC分类号： H01L21/4763

CPC分类号： H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： The embodiments provide a method for reducing electromigration in a circuit containing a through-silicon via (TSV) and the resulting novel structure for the TSV. A TSV is formed through a semiconductor substrate. A first end of the TSV connects to a first metallization layer on a device side of the semiconductor substrate. A second end of the TSV connects to a second metallization layer on a grind side of the semiconductor substrate. A first flat edge is created on the first end of the TSV at the intersection of the first end of the TSV and the first metallization layer. A second flat edge is created on the second end of the TSV at the intersection of the second end of the TSV and the second metallization layer. On top of the first end a metal contact grid is placed, having less than eighty percent metal coverage.

摘要翻译： 这些实施例提供了一种用于减少包含硅通孔（TSV）的电路中的电迁移的方法以及用于TSV的所得新颖结构。 通过半导体衬底形成TSV。 TSV的第一端连接到半导体衬底的器件侧上的第一金属化层。 TSV的第二端连接到半导体衬底的研磨侧的第二金属化层。 在TSV的第一端和第一金属化层的交叉点的TSV的第一端上形成第一平坦边缘。 在TSV的第二端和第二金属化层的交叉点的TSV的第二端上形成第二平坦边缘。 在第一端的顶部放置金属接触网格，金属覆盖率低于百分之八十。

公开(公告)号：US20120199975A1

公开(公告)日：2012-08-09

申请号：US13023743

申请日：2011-02-09

申请人： Mukta G. Farooq ,  John A. Griesemer ,  Gary LaFontant ,  William Francis Landers ,  Timothy Dooling Sullivan

发明人： Mukta G. Farooq ,  John A. Griesemer ,  Gary LaFontant ,  William Francis Landers ,  Timothy Dooling Sullivan

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： The embodiments provide a method for reducing electromigration in a circuit containing a through-silicon via (TSV) and the resulting novel structure for the TSV. A TSV is formed through a semiconductor substrate. A first end of the TSV connects to a first metallization layer on a device side of the semiconductor substrate. A second end of the TSV connects to a second metallization layer on a grind side of the semiconductor substrate. A first flat edge is created on the first end of the TSV at the intersection of the first end of the TSV and the first metallization layer. A second flat edge is created on the second end of the TSV at the intersection of the second end of the TSV and the second metallization layer. On top of the first end a metal contact grid is placed, having less than eighty percent metal coverage.

公开(公告)号：US20120199983A1

公开(公告)日：2012-08-09

申请号：US13397004

申请日：2012-02-15

申请人： Mukta G. Farooq ,  John A. Griesemer ,  Gary LaFontant ,  William Francis Landers ,  Timothy Dooling Sullivan

发明人： Mukta G. Farooq ,  John A. Griesemer ,  Gary LaFontant ,  William Francis Landers ,  Timothy Dooling Sullivan

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： The embodiments provide a method for reducing electromigration in a circuit containing a through-silicon via (TSV) and the resulting novel structure for the TSV. A TSV is formed through a semiconductor substrate. A first end of the TSV connects to a first metallization layer on a device side of the semiconductor substrate. A second end of the TSV connects to a second metallization layer on a grind side of the semiconductor substrate. A first flat edge is created on the first end of the TSV at the intersection of the first end of the TSV and the first metallization layer. A second flat edge is created on the second end of the TSV at the intersection of the second end of the TSV and the second metallization layer. On top of the first end a metal contact grid is placed, having less than eighty percent metal coverage.

摘要翻译： 这些实施例提供了一种用于减少包含硅通孔（TSV）的电路中的电迁移的方法以及用于TSV的所得新颖结构。 通过半导体衬底形成TSV。 TSV的第一端连接到半导体衬底的器件侧上的第一金属化层。 TSV的第二端连接到半导体衬底的研磨侧的第二金属化层。 在TSV的第一端和第一金属化层的交叉点的TSV的第一端上形成第一平坦边缘。 在TSV的第二端和第二金属化层的交叉点的TSV的第二端上形成第二平坦边缘。 在第一端的顶部放置金属接触网格，金属覆盖率低于百分之八十。

公开(公告)号：US20070008049A1

公开(公告)日：2007-01-11

申请号：US11160785

申请日：2005-07-08

申请人： Warren Dyckman ,  Gary LaFontant ,  Edward Pillai

发明人： Warren Dyckman ,  Gary LaFontant ,  Edward Pillai

IPC分类号： H01P5/02

CPC分类号： H05K1/115 ,  G06F17/5036 ,  G06F17/5068 ,  H05K1/0237 ,  H05K1/116 ,  H05K3/0005 ,  H05K2201/09236 ,  H05K2201/09718

摘要： The present invention provides a technique for adjusting the size of clearance holes for impedance control in multilayer electronic packaging and printed circuit boards. The method comprises: providing parameters for a structure having a clearance hole and at least one via passing through the clearance hole; calculating a characteristic impedance for the at least one via; and adjusting at least a size of the clearance hole until the characteristic impedance for the at least one via is approximately equal to a desired characteristic impedance.

摘要翻译： 本发明提供一种用于调整多层电子封装和印刷电路板中用于阻抗控制的间隙孔尺寸的技术。 该方法包括：为具有间隙孔和穿过间隙孔的至少一个通孔的结构提供参数; 计算所述至少一个通孔的特征阻抗; 以及至少调节所述间隙孔的尺寸，直到所述至少一个通孔的特征阻抗近似等于期望的特性阻抗。