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    Dynamic, Non-invasive detection of hot-pluggable problem components and re-active re-allocation of system resources from problem components
    1.
    发明授权
    Dynamic, Non-invasive detection of hot-pluggable problem components and re-active re-allocation of system resources from problem components 有权
    动态，非侵入式检测热插拔问题组件，并从问题组件重新分配系统资源

    公开(公告)号：US07117388B2

    公开(公告)日：2006-10-03

    申请号：US10424278

    申请日：2003-04-28

    申请人： Ravi Kumar Arimilli ,  Michael Stephen Floyd ,  Kevin Franklin Reick

    发明人： Ravi Kumar Arimilli ,  Michael Stephen Floyd ,  Kevin Franklin Reick

    IPC分类号： G06F11/00

    CPC分类号： G06F11/2043 ,  G06F11/2028 ,  G06F11/2289

    摘要： A method, system, and data processing system for dynamic detection of problem components in a hot-plug processing system and automatic removal of the problem component via hot-removal methods without disrupting processing of the overall system. A data processing system that provides a non-disruptive, hot-plug functionality is designed with a additional logic for initiating and/or completing a sequence of factory level tests on hot-pluggable components to determine if the component if functioning properly. When a component is not functioning properly, the OS re-allocates the workload of the component to other component so the system, and when the OS completes the re-allocation, the service element initiates the hot removal of the component so that the component is logically and electrically separated from the system.

    摘要翻译： 一种用于动态检测热插拔处理系统中的问题组件的方法，系统和数据处理系统，并且通过热删除方法自动移除问题组件，而不会中断整个系统的处理。 提供无中断的热插拔功能的数据处理系统设计有一个额外的逻辑，用于启动和/或完成热插拔组件上的一系列工厂级测试，以确定组件是否正常工作。 当组件运行不正常时，操作系统将组件的工作负载重新分配给其他组件，以便系统，并且当操作系统完成重新分配时，服务组件启动组件的热删除，以使组件 与系统逻辑和电气分离。

    Non-disruptive, dynamic hot-plug and hot-remove of server nodes in an SMP
    2.
    发明授权
    Non-disruptive, dynamic hot-plug and hot-remove of server nodes in an SMP 有权
    SMP中服务器节点的无中断，动态热插拔和热删除

    公开(公告)号：US06990545B2

    公开(公告)日：2006-01-24

    申请号：US10424277

    申请日：2003-04-28

    申请人： Ravi Kumar Arimilli ,  Michael Stephen Floyd ,  Kevin Franklin Reick

    发明人： Ravi Kumar Arimilli ,  Michael Stephen Floyd ,  Kevin Franklin Reick

    IPC分类号： G06F13/00

    CPC分类号： G06F13/4081

    摘要： A data processing system that provides hot-plug add and remove functionality for individual, hot-pluggable components without disrupting current operations of the overall processing system. The processing system includes an interconnect fabric that includes hot plug connector at which an external hot-pluggable component can be coupled to the data processing system and logic components include configuration logic and routing and operating logic. When a hot-pluggable component is connected to the hot plug connector, the service element automatically detects the connection and selects the correct configuration file for the extended system. Once the configuration file is loaded and the system checks of the new element indicates the new element is ready for integration, the new element is integrated into the existing system, and the OS allocates workload to the new element. From a customer perspective, the entire process thus occurs without powering down or disrupting the operation of the existing element.

    摘要翻译： 一种数据处理系统，可为单个热插拔组件提供热插拔添加和删除功能，而不会中断整个处理系统的当前操作。 处理系统包括互连结构，其包括热插拔连接器，外部可热插拔组件可以连接到数据处理系统，逻辑组件包括配置逻辑和路由和操作逻辑。 当热插拔组件连接到热插拔连接器时，服务元件会自动检测连接并为扩展系统选择正确的配置文件。 一旦加载了配置文件，并且新元素的系统检查指示新元素可以进行集成，则将新元素集成到现有系统中，并且操作系统将工作负载分配给新元素。 从客户的角度来看，整个过程都是在不掉电或破坏现有元素的操作的情况下进行的。

    Techniques for dynamically assigning jobs to processors in a cluster based on broadcast information
    4.
    发明授权
    Techniques for dynamically assigning jobs to processors in a cluster based on broadcast information 有权
    基于广播信息将作业动态地分配给集群中的处理器的技术

    公开(公告)号：US08122132B2

    公开(公告)日：2012-02-21

    申请号：US12336312

    申请日：2008-12-16

    申请人： Lakshminarayana Baba Arimilli ,  Ravi Kumar Arimilli ,  Claude Basso ,  Jean L. Calvignac

    发明人： Lakshminarayana Baba Arimilli ,  Ravi Kumar Arimilli ,  Claude Basso ,  Jean L. Calvignac

    IPC分类号： G06F13/00

    CPC分类号： G06F9/5088

    摘要： A technique for operating a high performance computing cluster (HPC) having multiple nodes (each of which include multiple processors) includes periodically broadcasting information, related to processor utilization and network utilization at each of the multiple nodes, from each of the multiple nodes to remaining ones of the multiple nodes. Respective local job tables maintained in each of the multiple nodes are updated based on the broadcast information. One or more threads are then moved from one or more of the multiple processors to a different one of the multiple processors (based on the broadcast information in the respective local job tables).

    摘要翻译： 用于操作具有多个节点（每个包括多个处理器）的高性能计算群集（HPC）的技术包括：从多个节点中的每个节点到多个节点周期性地广播与多个节点中的每个节点处的处理器利用和网络利用相关的信息 多个节点中的一个。 基于广播信息来更新维护在多个节点中的每个节点的相应的本地作业表。 然后，一个或多个线程从多个处理器中的一个或多个移动到多个处理器中的不同处理器（基于相应的本地作业表中的广播信息）。

    Dynamic Runtime Modification of Array Layout for Offset
    5.
    发明申请
    Dynamic Runtime Modification of Array Layout for Offset 有权
    用于偏移的阵列布局的动态运行时修改

    公开(公告)号：US20100268880A1

    公开(公告)日：2010-10-21

    申请号：US12424348

    申请日：2009-04-15

    申请人： Ravi Kumar Arimilli ,  Donald W. Plass ,  William John Starke

    发明人： Ravi Kumar Arimilli ,  Donald W. Plass ,  William John Starke

    IPC分类号： G06F12/08 ,  G06F1/12

    CPC分类号： G06F12/0886 ,  G06F9/30047 ,  G06F9/345

    摘要： Disclosed are a method, a system and a computer program product for operating a cache system. The cache system can include multiple cache lines, and a first cache line of the multiple of cache lines can include multiple cache cells, and a bus coupled to the multiple cache cells. In one or more embodiments, the bus can include a switch that is operable to receive a first control signal and to split the bus into first and second portions or aggregate the bus into a whole based on the first control signal. When the bus is split, a first cache cell and a second cache cell of the multiple cache cells are coupled to respective first and second portions of the bus. Data from the first and second cache cells can be selected through respective portions of the bus and outputted through a port of the cache system.

    摘要翻译： 公开了一种用于操作缓存系统的方法，系统和计算机程序产品。 高速缓存系统可以包括多个高速缓存行，并且多条高速缓存行的第一高速缓存行可以包括多个高速缓存单元，以及耦合到多个高速缓存单元的总线。 在一个或多个实施例中，总线可以包括可操作以接收第一控制信号并且将总线分为第一和第二部分或基于第一控制信号将总线聚合成整体的开关。 当总线被分离时，多个高速缓存单元的第一高速缓存单元和第二高速缓存单元耦合到总线的相应的第一和第二部分。 可以通过总线的各个部分选择来自第一和第二高速缓存单元的数据，并通过高速缓存系统的端口输出。

    Method and data processing system for microprocessor communication in a cluster-based multi-processor system
    6.
    发明授权
    Method and data processing system for microprocessor communication in a cluster-based multi-processor system 失效
    基于群集的多处理器系统中微处理器通信的方法和数据处理系统

    公开(公告)号：US07818364B2

    公开(公告)日：2010-10-19

    申请号：US11952479

    申请日：2007-12-07

    申请人： Ravi Kumar Arimilli ,  Robert Alan Cargnoni ,  Derek Edward Williams ,  Kenneth Lee Wright

    发明人： Ravi Kumar Arimilli ,  Robert Alan Cargnoni ,  Derek Edward Williams ,  Kenneth Lee Wright

    IPC分类号： G06F15/76 ,  G06F15/163

    CPC分类号： H04L69/16 ,  G06F15/17 ,  H04L12/42 ,  H04L67/1002 ,  H04L69/161 ,  H04W28/14

    摘要： A processor communication register (PCR) contained within a multiprocessor cluster system provides enhanced processor communication. The PCR stores information that is useful in pipelined or parallel multi-processing. Each processor cluster has exclusive rights to store to a sector within the PCR and has continuous access to read its contents. Each processor cluster updates its exclusive sector within the PCR, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the processor cluster network by providing processor communications to be immediately networked and transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.

    摘要翻译： 包含在多处理器集群系统内的处理器通信寄存器（PCR）提供增强的处理器通信。 PCR存储在流水线或并行多处理中有用的信息。 每个处理器集群具有存储到PCR中的扇区的独占权限，并且具有连续访问以读取其内容。 每个处理器集群在PCR中更新其独占部分，立即允许集群网络内的所有其他处理器查看PCR数据中的更改，并绕过缓存子系统。 处理器集群网络中的效率得到提高，通过提供处理器通信来立即联网并传输到所有处理器中，而不会立即限制对信息的访问，或迫使所有处理器持续竞争相同的高速缓存行，从而压倒互连和内存 系统具有无限的加载流，存储和无效命令。

    Multiprocessor system with retry-less TLBI protocol
    8.
    发明授权
    Multiprocessor system with retry-less TLBI protocol 失效
    具有重试TLBI协议的多处理器系统

    公开(公告)号：US07617378B2

    公开(公告)日：2009-11-10

    申请号：US10425402

    申请日：2003-04-28

    申请人： Ravi Kumar Arimilli ,  Guy Lynn Guthrie ,  Kirk Samuel Livingston

    发明人： Ravi Kumar Arimilli ,  Guy Lynn Guthrie ,  Kirk Samuel Livingston

    IPC分类号： G06F12/00

    CPC分类号： G06F12/1027 ,  G06F2212/682 ,  G06F2212/683

    摘要： A symmetric multiprocessor data processing system (SMP) that implements a TLBI protocol, which enables multiple TLBI operations from multiple processors to complete without causing delay. Each processor includes a TLBI register associated with the TLB and TLBI logic. The TLBI register includes a sequence of bits utilized to track the completion of a TLBI issued by the processor at the other processors. Each bit corresponds to a particular processor across the system and the particular processor is able to directly set the bit in the register of a master processor once the particular processor completes a TLBI operation initiated from the master processor. The master processor is able to track completion of the TLBI operation by checking the values of each bit within its TLBI register, without requiring multi-issuance of an address-only barrier operation on the system bus.

    摘要翻译： 实现TLBI协议的对称多处理器数据处理系统（SMP），使多个处理器的多个TLBI操作能够完成而不会造成延迟。 每个处理器包括与TLB和TLBI逻辑相关联的TLBI寄存器。 TLBI寄存器包括用于跟踪由处理器在其他处理器发出的TLBI的完成的位的序列。 每个位对应于跨系统的特定处理器，并且特定处理器能够在特定处理器完成从主处理器发起的TLBI操作之后直接设置主处理器的寄存器中的位。 主处理器能够通过检查其TLBI寄存器中每个位的值来跟踪完成TLBI操作，而不需要在系统总线上多次发出仅地址唯一的屏蔽操作。

    Method and data processing system optimizing performance through reporting of thread-level hardware resource utilization
    10.
    发明授权
    Method and data processing system optimizing performance through reporting of thread-level hardware resource utilization 失效
    方法和数据处理系统通过报告线程级硬件资源利用率来优化性能

    公开(公告)号：US07475399B2

    公开(公告)日：2009-01-06

    申请号：US10755877

    申请日：2004-01-13

    申请人： Ravi Kumar Arimilli ,  Randal Craig Swanberg

    发明人： Ravi Kumar Arimilli ,  Randal Craig Swanberg

    IPC分类号： G06F9/46 ,  G06F9/30

    CPC分类号： G06F11/3466 ,  G06F2201/88

    摘要： According to a method of operating a data processing system, one or more monitoring parameter sets are established in a processing unit within the data processing system. The processing unit monitors, in hardware, execution of each of a plurality of schedulable software entities within the processing unit in accordance with a monitoring parameter set among the one or more monitoring parameter sets. The processing unit then reports to software executing in the data processing system utilization of hardware resources by each of the plurality of schedulable software entities. The hardware utilization information reported by the processing unit may be stored and utilized by software to schedulable execution of the schedulable software entities reported by the processing unit. The hardware utilization information may also be utilized to generate a classification of at least one executing schedulable software entity, which may be communicated to the processing unit to dynamically modify an allocation of hardware resources to the schedulable software entity.

    摘要翻译： 根据操作数据处理系统的方法，在数据处理系统内的处理单元中建立一个或多个监视参数组。 处理单元根据在一个或多个监视参数组中设置的监视参数，硬件地监视处理单元内的多个可调度软件实体中的每一个的执行。 然后，处理单元通过多个可调度软件实体中的每一个向硬件资源的数据处理系统利用执行的软件报告。 由处理单元报告的硬件利用信息可由软件存储和利用，以便可处理单元报告的可调度软件实体的可调度执行。 还可以利用硬件利用信息来生成至少一个执行的可调度软件实体的分类，所述可执行可调度软件实体可以被传送到处理单元以动态地修改对可调度软件实体的硬件资源的分配。