公开(公告)号：US10268250B2

公开(公告)日：2019-04-23

申请号：US15649051

申请日：2017-07-13

Applicant: Renesas Electronics Corporation

Inventor： Hiromi Notani ,  Takayuki Fukuoka ,  Takashi Yamaki

IPC: G06F1/26

Abstract: A semiconductor device having an active mode and a standby mode as operation modes, includes a first power supply line supplied with a first internal power supply voltage from a first external power supply and an internal power supply circuit generating a second internal power supply voltage based on an external power supply voltage from a second external power supply circuit. A second power supply line supplied with said second internal power supply voltage from said internal power supply circuit.

公开(公告)号：US09727106B2

公开(公告)日：2017-08-08

申请号：US14134537

申请日：2013-12-19

Applicant: Renesas Electronics Corporation

Inventor： Hiromi Notani ,  Takayuki Fukuoka ,  Takashi Yamaki

IPC: G06F1/26

CPC classification number: G06F1/263

Abstract: In an active mode, a VDD line receives an internal power supply voltage from an external regulator. A VDD_RAM line receives an internal power supply voltage from an internal regulator. A PMOS switch includes a first PMOS transistor having a source and an N-type well connected to the VDD line, and a second PMOS transistor having a source and an N-type well connected to the VDD_RAM line and a drain connected to a drain of the first PMOS transistor. The first PMOS transistor is controlled based on a control command from a system control circuit and a voltage of the VDD_RAM line. The second PMOS transistor is controlled based on the control command and a voltage of the VDD line.

公开(公告)号：US09274537B2

公开(公告)日：2016-03-01

申请号：US14563790

申请日：2014-12-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiromi Notani

IPC: G05F1/10 ,  G05F1/575

CPC classification number: G05F1/575 ,  G05F1/10

Abstract: There is provided a regulator circuit capable of increasing the capacity of the output transistor for supplying current, stably generating an internal power supply voltage and adapting to the reduction of a power supply voltage. The regulator circuit includes an output transistor which is supplied with an external power supply voltage and supplies dropped voltage to an internal circuit, a differential amplifier for outputting a gate potential applied to the gate of the output transistor, a reference voltage generating circuit for supplying a reference voltage to the differential amplifier, and a cut-off transistor for turning off the output transistor to stop supplying power to the internal circuit. The output transistor is comprised of a depression NMOS transistor whose threshold voltage is a negative voltage. The regulator circuit further includes substrate potential control means for controlling the substrate potential of the depression NMOS transistor.

公开(公告)号：US20170083080A1

公开(公告)日：2017-03-23

申请号：US15370718

申请日：2016-12-06

Applicant: Renesas Electronics Corporation

Inventor： Soichi Kobayashi ,  Akira Oizumi ,  Yoshihiko Yasu ,  Hiromi Notani

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G05F1/56 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3296 ,  G11C5/147 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/172 ,  Y02D50/20

Abstract: A data processing device includes a load circuit including a central processing unit and operated by supplied electric power, a step-down power supply circuit stepping down an external power supply voltage and including an output node coupled to the load circuit, the step-down power supply circuit including a first step-down unit stepping down the external power supply voltage, and a bias current control circuit controlling a magnitude of bias current flowing through an auxiliary path from the output node to a ground, the auxiliary path is separate from a path to the load circuit, and a control circuit increasing the magnitude of the bias current, prior to a change of an operation state of the load circuit by which a relatively large change occurs to an amount of current consumed by the load circuit.

公开(公告)号：US10317981B2

公开(公告)日：2019-06-11

申请号：US15370718

申请日：2016-12-06

Applicant: Renesas Electronics Corporation

Inventor： Soichi Kobayashi ,  Akira Oizumi ,  Yoshihiko Yasu ,  Hiromi Notani

IPC: G06F1/3287 ,  G06F1/324 ,  G06F1/3206 ,  G06F1/3237 ,  G06F1/3234 ,  G06F1/3296 ,  G06F1/3203 ,  G06F1/32 ,  G11C5/14 ,  G05F1/56

Abstract: A data processing device includes a load circuit including a central processing unit and operated by supplied electric power, a step-down power supply circuit stepping down an external power supply voltage and including an output node coupled to the load circuit, the step-down power supply circuit including a first step-down unit stepping down the external power supply voltage, and a bias current control circuit controlling a magnitude of bias current flowing through an auxiliary path from the output node to a ground, the auxiliary path is separate from a path to the load circuit, and a control circuit increasing the magnitude of the bias current, prior to a change of an operation state of the load circuit by which a relatively large change occurs to an amount of current consumed by the load circuit.

公开(公告)号：US20170308138A1

公开(公告)日：2017-10-26

申请号：US15649051

申请日：2017-07-13

Applicant: Renesas Electronics Corporation

Inventor： Hiromi Notani ,  Takayuki Fukuoka ,  Takashi Yamaki

IPC: G06F1/26

CPC classification number: G06F1/263

Abstract: A semiconductor device having an active mode and a standby mode as operation modes, includes a first power supply line supplied with a first internal power supply voltage from a first external power supply and an internal power supply circuit generating a second internal power supply voltage based on an external power supply voltage from a second external power supply circuit.A second power supply line supplied with said second internal power supply voltage from said internal power supply circuit.

公开(公告)号：US08917071B2

公开(公告)日：2014-12-23

申请号：US13861254

申请日：2013-04-11

Applicant: Renesas Electronics Corporation

Inventor： Hiromi Notani

IPC: G05F1/40 ,  G05F3/02

CPC classification number: G05F1/575 ,  G05F1/10

Abstract: There is provided a regulator circuit capable of increasing the capacity of the output transistor for supplying current, stably generating an internal power supply voltage and adapting to the reduction of a power supply voltage. The regulator circuit includes an output transistor which is supplied with an external power supply voltage and supplies dropped voltage to an internal circuit, a differential amplifier for outputting a gate potential applied to the gate of the output transistor, a reference voltage generating circuit for supplying a reference voltage to the differential amplifier, and a cut-off transistor for turning off the output transistor to stop supplying power to the internal circuit. The output transistor is comprised of a depression NMOS transistor whose threshold voltage is a negative voltage. The regulator circuit further includes substrate potential control means for controlling the substrate potential of the depression NMOS transistor.

Abstract translation: 提供了一种调节器电路，其能够增加用于提供电流的输出晶体管的容量，稳定地产生内部电源电压并适应于降低电源电压。 调节器电路包括输出晶体管，其被提供有外部电源电压并向内部电路提供下降的电压;差分放大器，用于输出施加到输出晶体管的栅极的栅极电位;基准电压产生电路， 参考电压到差分放大器，以及截止晶体管，用于截止输出晶体管以停止向内部电路供电。 输出晶体管由阈值电压为负电压的抑制NMOS晶体管组成。 调节器电路还包括用于控制凹陷NMOS晶体管的衬底电位的衬底电位控制装置。

公开(公告)号：US20140189381A1

公开(公告)日：2014-07-03

申请号：US14134537

申请日：2013-12-19

Applicant: Renesas Electronics Corporation

Inventor： Hiromi Notani ,  Takayuki Fukuoka ,  Takashi Yamaki

IPC: G06F1/26

CPC classification number: G06F1/263

Abstract: In an active mode, a VDD line receives an internal power supply voltage from an external regulator. A VDD_RAM line receives an internal power supply voltage from an internal regulator. A PMOS switch includes a first PMOS transistor having a source and an N-type well connected to the VDD line, and a second PMOS transistor having a source and an N-type well connected to the VDD_RAM line and a drain connected to a drain of the first PMOS transistor. The first PMOS transistor is controlled based on a control command from a system control circuit and a voltage of the VDD_RAM line. The second PMOS transistor is controlled based on the control command and a voltage of the VDD line.

Abstract translation: 在有源模式下，VDD线从外部稳压器接收内部电源电压。 VDD_RAM线从内部稳压器接收内部电源电压。 PMOS开关包括具有源极和连接到VDD线的N型阱的第一PMOS晶体管和具有连接到VDD_RAM线的源极和N型阱的第二PMOS晶体管，以及连接到VDD线的漏极的漏极 第一个PMOS晶体管。 基于来自系统控制电路的控制命令和VDD_RAM线的电压来控制第一PMOS晶体管。 基于控制命令和VDD线的电压来控制第二PMOS晶体管。