公开(公告)号：US09443991B2

公开(公告)日：2016-09-13

申请号：US15062160

申请日：2016-03-06

Applicant: Renesas Electronics Corporation

Inventor： Kota Funayama ,  Hiraku Chakihara ,  Yasushi Ishii

IPC: H01L29/792 ,  H01L29/423 ,  H01L29/06 ,  H01L23/535 ,  H01L23/532 ,  H01L27/115

CPC classification number: H01L29/792 ,  H01L21/28273 ,  H01L21/28282 ,  H01L23/53214 ,  H01L23/53257 ,  H01L23/535 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/0653 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/7831 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a power feeding region of a memory cell (MC) in which a sidewall-shaped memory gate electrode (MG) of a memory nMIS (Qnm) is provided by self alignment on a side surface of a selection gate electrode (CG) of a selection nMIS (Qnc) via an insulating film, a plug (PM) which supplies a voltage to the memory gate electrode (MG) is embedded in a contact hole (CM) formed in an interlayer insulating film (9) formed on the memory gate electrode (MG) and is electrically connected to the memory gate electrode (MG). Since a cap insulating film (CAP) is formed on an upper surface of the selection gate electrode (CG), the electrical conduction between the plug (PM) and the selection gate electrode (CG) can be prevented.

Abstract translation: 在存储单元（MC）的馈电区域中，在存储单元（MC）的馈电区域中，通过自对准在存储器nMIS（Qnm）的选择栅极（CG）的侧表面上提供存储器nMIS（Qnm）的侧壁形状的存储栅极（MG） 通过绝缘膜选择nMIS（Qnc），向存储栅电极（MG）提供电压的插头（PM）嵌入在形成在存储栅上的层间绝缘膜（9）中形成的接触孔（CM） 电极（MG）并且电连接到存储栅电极（MG）。 由于在选择栅电极（CG）的上表面上形成帽绝缘膜（CAP），所以可以防止插头（PM）与选择栅电极（CG）之间的导电。

公开(公告)号：US20150325583A1

公开(公告)日：2015-11-12

申请号：US14803060

申请日：2015-07-18

Applicant: Renesas Electronics Corporation

Inventor： Kota Funayama ,  Hiraku Chakihara ,  Yasushi Ishii

IPC: H01L27/115

CPC classification number: H01L27/11563 ,  G11C16/0466 ,  H01L27/1052 ,  H01L27/11517 ,  H01L27/11565 ,  H01L27/11568 ,  H01L28/40 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/66477 ,  H01L29/66833 ,  H01L29/792

Abstract: A memory cell of a nonvolatile memory and a capacitive element are formed over the same semiconductor substrate. The memory cell includes a control gate electrode formed over the semiconductor substrate via a first insulating film, a memory gate electrode formed adjacent to the control gate electrode over the semiconductor substrate via a second insulating film, and the second insulating film having therein a charge storing portion. The capacitive element includes a lower electrode formed of the same layer of a silicon film as the control gate electrode, a capacity insulating film formed of the same insulating film as the second insulating film, and an upper electrode formed of the same layer of a silicon film as the memory gate electrode. The concentration of impurities of the upper electrode is higher than that of the memory gate electrode.

Abstract translation: 在相同的半导体衬底上形成非易失性存储器和电容元件的存储单元。 存储单元包括经由第一绝缘膜形成在半导体衬底上的控制栅极电极，经由第二绝缘膜在半导体衬底上与控制栅电极相邻形成的存储栅电极，并且其中具有电荷存储的第二绝缘膜 一部分。 电容元件包括由与控制栅电极相同的硅膜层形成的下电极，由与第二绝缘膜相同的绝缘膜形成的电容绝缘膜和由相同的硅层形成的上电极 薄膜作为记忆栅电极。 上部电极的杂质浓度高于记忆栅电极的浓度。

公开(公告)号：US20150287736A1

公开(公告)日：2015-10-08

申请号：US14745340

申请日：2015-06-19

Applicant: Renesas Electronics Corporation

Inventor： Koichi Toba ,  Yasushi Ishii ,  Hiraku Chakihara ,  Kota Funayama ,  Yoshiyuki Kawashima ,  Takashi Hashimoto

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/792

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/792

Abstract: A semiconductor device with a nonvolatile memory is provided which has improved characteristics. The semiconductor device includes a control gate electrode, a memory gate electrode disposed adjacent to the control gate electrode, a first insulating film, and a second insulating film including therein a charge storing portion. Among these components, the memory gate electrode is formed of a silicon film including a first silicon region positioned over the second insulating film,. and a second silicon region positioned above the first silicon region. The second silicon region contains p-type impurities, and the concentration of p-type impurities of the first silicon region is lower than that of the p-type impurities of the second silicon region.

Abstract translation: 提供了具有非易失性存储器的半导体器件，其具有改进的特性。 半导体器件包括控制栅极电极，与控制栅电极相邻设置的存储栅电极，第一绝缘膜和包括电荷存储部分的第二绝缘膜。 在这些部件中，存储栅电极由包括位于第二绝缘膜上的第一硅区的硅膜形成。 以及位于第一硅区上方的第二硅区。 第二硅区域含有p型杂质，第一硅区域的p型杂质浓度低于第二硅区域的p型杂质浓度。

公开(公告)号：US09093546B2

公开(公告)日：2015-07-28

申请号：US14066740

申请日：2013-10-30

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi Uozaki ,  Yasuhiro Takeda ,  Keiichi Maekawa ,  Takumi Hasegawa ,  Kota Funayama ,  Yoshiki Maruyama ,  Kazutoshi Shiba ,  Shuichi Kudo

IPC: H01L29/788 ,  H01L27/11 ,  H01L21/28 ,  H01L27/105 ,  H01L27/115 ,  H01L29/423 ,  H01L29/792

CPC classification number: H01L29/788 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/1104 ,  H01L27/11573 ,  H01L29/401 ,  H01L29/42344 ,  H01L29/792

Abstract: An object is to provide a semiconductor device having improved reliability by preventing, in forming a nonvolatile memory and MOSFETS on the same substrate, an increase in the size of grains in a gate electrode. The object can be achieved by forming the control gate electrode of the nonvolatile memory and the gate electrodes of the other MOSFETs from films of the same layer, respectively, and configuring each of the control gate electrode and the gate electrodes from a stack of two polysilicon film layers.

Abstract translation: 本发明的目的是通过在同一基板上形成非易失性存储器和MOSFETS来防止栅极电极中的晶粒尺寸的增加来提供具有改善的可靠性的半导体器件。 可以通过分别从相同层的膜形成非易失性存储器的控制栅电极和其它MOSFET的栅电极并且从两个多晶硅的堆叠中配置每个控制栅电极和栅电极来实现该目的 电影层。

公开(公告)号：US08853036B2

公开(公告)日：2014-10-07

申请号：US14138036

申请日：2013-12-21

Applicant: Renesas Electronics Corporation

Inventor： Kota Funayama ,  Hiraku Chakihara ,  Yasushi Ishii

IPC: H01L29/66 ,  H01L21/28 ,  H01L27/115 ,  H01L29/423

CPC classification number: H01L29/792 ,  H01L21/28273 ,  H01L21/28282 ,  H01L23/53214 ,  H01L23/53257 ,  H01L23/535 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/0653 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/7831 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a power feeding region of a memory cell (MC) in which a sidewall-shaped memory gate electrode (MG) of a memory nMIS (Qnm) is provided by self alignment on a side surface of a selection gate electrode (CG) of a selection nMIS (Qnc) via an insulating film, a plug (PM) which supplies a voltage to the memory gate electrode (MG) is embedded in a contact hole (CM) formed in an interlayer insulating film (9) formed on the memory gate electrode (MG) and is electrically connected to the memory gate electrode (MG). Since a cap insulating film (CAP) is formed on an upper surface of the selection gate electrode (CG), the electrical conduction between the plug (PM) and the selection gate electrode (CG) can be prevented.

公开(公告)号：US09379127B2

公开(公告)日：2016-06-28

申请号：US14745340

申请日：2015-06-19

Applicant: Renesas Electronics Corporation

Inventor： Koichi Toba ,  Yasushi Ishii ,  Hiraku Chakihara ,  Kota Funayama ,  Yoshiyuki Kawashima ,  Takashi Hashimoto

IPC: H01L29/792 ,  H01L27/115 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/792

Abstract: A semiconductor device with a nonvolatile memory is provided which has improved characteristics. The semiconductor device includes a control gate electrode, a memory gate electrode disposed adjacent to the control gate electrode, a first insulating film, and a second insulating film including therein a charge storing portion. Among these components, the memory gate electrode is formed of a silicon film including a first silicon region positioned over the second insulating film, and a second silicon region positioned above the first silicon region. The second silicon region contains p-type impurities, and the concentration of p-type impurities of the first silicon region is lower than that of the p-type impurities of the second silicon region.

公开(公告)号：US20150333139A1

公开(公告)日：2015-11-19

申请号：US14803037

申请日：2015-07-18

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi Uozaki ,  Yasuhiro Takeda ,  Keiichi Maekawa ,  Takumi Hasegawa ,  Kota Funayama ,  Yoshiki Maruyama ,  Kazutoshi Shiba ,  Shuichi Kudo

IPC: H01L29/423 ,  H01L29/40

CPC classification number: H01L29/788 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/1104 ,  H01L27/11573 ,  H01L29/401 ,  H01L29/42344 ,  H01L29/792

Abstract: An object is to provide a semiconductor device having improved reliability by preventing, in forming a nonvolatile memory and MOSFETS on the same substrate, an increase in the size of grains in a gate electrode. The object can be achieved by forming the control gate electrode of the nonvolatile memory and the gate electrodes of the other MOSFETs from films of the same layer, respectively, and configuring each of the control gate electrode and the gate electrodes from a stack of two polysilicon film layers.

Abstract translation: 本发明的目的是通过在同一基板上形成非易失性存储器和MOSFETS来防止栅极电极中的晶粒尺寸的增加来提供具有改善的可靠性的半导体器件。 可以通过分别从相同层的膜形成非易失性存储器的控制栅电极和其它MOSFET的栅电极并且从两个多晶硅的堆叠中配置每个控制栅电极和栅电极来实现该目的 电影层。

公开(公告)号：US20140138758A1

公开(公告)日：2014-05-22

申请号：US14066740

申请日：2013-10-30

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi Uozaki ,  Yasuhiro Takeda ,  Keiichi Maekawa ,  Takumi Hasegawa ,  Kota Funayama ,  Yoshiki Maruyama ,  Kazutoshi Shiba ,  Shuichi Kudo

IPC: H01L29/423 ,  H01L29/788 ,  H01L27/11 ,  H01L21/28

CPC classification number: H01L29/788 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/1104 ,  H01L27/11573 ,  H01L29/401 ,  H01L29/42344 ,  H01L29/792

Abstract: An object is to provide a semiconductor device having improved reliability by preventing, in forming a nonvolatile memory and MOSFETS on the same substrate, an increase in the size of grains in a gate electrode. The object can be achieved by forming the control gate electrode of the nonvolatile memory and the gate electrodes of the other MOSFETs from films of the same layer, respectively, and configuring each of the control gate electrode and the gate electrodes from a stack of two polysilicon film layers.

Abstract translation: 本发明的目的是通过在同一基板上形成非易失性存储器和MOSFETS来防止栅极电极中的晶粒尺寸的增加来提供具有改善的可靠性的半导体器件。 可以通过分别从相同层的膜形成非易失性存储器的控制栅电极和其它MOSFET的栅电极并且从两个多晶硅的堆叠中配置每个控制栅电极和栅电极来实现该目的 电影层。

公开(公告)号：US09356110B2

公开(公告)日：2016-05-31

申请号：US14173074

申请日：2014-02-05

Applicant: Renesas Electronics Corporation

Inventor： Masao Inoue ,  Yoshiki Maruyama ,  Akio Nishida ,  Yorinobu Kunimune ,  Kota Funayama

IPC: H01L21/28 ,  H01L29/40 ,  H01L29/49 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/4925 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/28035 ,  H01L21/28176 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/4916 ,  H01L29/66825

Abstract: To control a grain growth on laminated polysilicon films, a method of manufacturing a semiconductor device is provided. The method includes: forming a first polysilicon film (21) on a substrate (10); forming an interlayer oxide layer (22) on a surface of the first polysilicon film (21); forming a second polysilicon film (23) in contact with the interlayer oxide layer (22) above the first polysilicon film (21); and performing annealing at a temperature higher than a film formation temperature of the first and second polysilicon films in a gas atmosphere containing nitrogen, after formation of the second polysilicon film (23).

Abstract translation: 为了控制层叠多晶硅膜上的晶粒生长，提供了制造半导体器件的方法。 该方法包括：在衬底（10）上形成第一多晶硅膜（21）; 在所述第一多晶硅膜（21）的表面上形成层间氧化物层（22）; 形成与第一多晶硅膜（21）上方的层间氧化物层（22）接触的第二多晶硅膜（23）。 在形成第二多晶硅膜（23）之后，在含氮气体气氛中，在高于第一和第二多晶硅膜的成膜温度的温度下进行退火。

公开(公告)号：US09324883B2

公开(公告)日：2016-04-26

申请号：US14479362

申请日：2014-09-07

Applicant: Renesas Electronics Corporation

Inventor： Kota Funayama ,  Hiraku Chakihara ,  Yasushi Ishii

IPC: H01L29/792 ,  H01L21/8239 ,  H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78

CPC classification number: H01L29/792 ,  H01L21/28273 ,  H01L21/28282 ,  H01L23/53214 ,  H01L23/53257 ,  H01L23/535 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/0653 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/7831 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a power feeding region of a memory cell (MC) in which a sidewall-shaped memory gate electrode (MG) of a memory nMIS (Qnm) is provided by self alignment on a side surface of a selection gate electrode (CG) of a selection nMIS (Qnc) via an insulating film, a plug (PM) which supplies a voltage to the memory gate electrode (MG) is embedded in a contact hole (CM) formed in an interlayer insulating film (9) formed on the memory gate electrode (MG) and is electrically connected to the memory gate electrode (MG). Since a cap insulating film (CAP) is formed on an upper surface of the selection gate electrode (CG), the electrical conduction between the plug (PM) and the selection gate electrode (CG) can be prevented.