公开(公告)号：US10115469B2

公开(公告)日：2018-10-30

申请号：US15796193

申请日：2017-10-27

申请人： Renesas Electronics Corporation

发明人： Toshihiro Tanaka ,  Yukiko Umemoto ,  Mitsuru Hiraki ,  Yutaka Shinagawa ,  Masamichi Fujito ,  Kazufumi Suzukawa ,  Hiroyuki Tanikawa ,  Takashi Yamaki ,  Yoshiaki Kamigaki ,  Shinichi Minami ,  Kozo Katayama ,  Nozomu Matsuzaki

IPC分类号： G11C16/26 ,  G11C5/02 ,  H01L29/788 ,  G11C8/08 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  H01L21/28 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  G11C16/04

摘要： A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc

公开(公告)号：US09812211B2

公开(公告)日：2017-11-07

申请号：US15224669

申请日：2016-08-01

申请人： Renesas Electronics Corporation

发明人： Toshihiro Tanaka ,  Yukiko Umemoto ,  Mitsuru Hiraki ,  Yutaka Shinagawa ,  Masamichi Fujito ,  Kazufumi Suzukawa ,  Hiroyuki Tanikawa ,  Takashi Yamaki ,  Yoshiaki Kamigaki ,  Shinichi Minami ,  Kozo Katayama ,  Nozomu Matsuzaki

IPC分类号： G11C16/10 ,  G11C16/26 ,  H01L21/28 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  G11C16/24 ,  G11C5/02 ,  G11C8/08 ,  G11C16/08 ,  G11C16/30 ,  G11C16/04

CPC分类号： G11C16/26 ,  G11C5/025 ,  G11C8/08 ,  G11C16/04 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  H01L21/28 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/7885 ,  H01L29/792

摘要： A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc

公开(公告)号：US09557790B2

公开(公告)日：2017-01-31

申请号：US15015643

申请日：2016-02-04

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Takashi Yamaki

IPC分类号： G11C5/02 ,  G06F1/26 ,  G11C5/14 ,  G11C7/22 ,  G11C11/413 ,  G06F3/06 ,  G11C11/417

CPC分类号： G11C11/419 ,  G06F1/26 ,  G06F3/0604 ,  G06F3/0629 ,  G06F3/067 ,  G11C5/148 ,  G11C7/22 ,  G11C11/413 ,  G11C11/417 ,  G11C11/418 ,  G11C2207/2227

摘要： In a semiconductor device, memory modules each having a low power consumption mode that is enabled and disabled by a control signal belong to a memory block. A transmission path of the control signal is provided such that the control signal is inputted in parallel to the memory module via an inside-of-module path, and such that the control signal is outputted by a particular memory module of the memory modules via the inside-of-module path to a downstream outside-of-module path. The particular memory module in the memory block is selected such that it has a greater storage capacity than the other memory modules belonging to this same memory block have.

摘要翻译： 在半导体装置中，各自具有由控制信号启用和禁用的低功耗模式的存储器模块属于存储块。 提供控制信号的传输路径，使得控制信号经由内部模块路径并行地输入到存储器模块，并且使得控制信号由存储器模块的特定存储器模块经由 模块内部路径到模块下游的路径。 选择存储器块中的特定存储器模块使得其具有比属于该相同存储器块的其它存储器模块更大的存储容量。

公开(公告)号：US20170308138A1

公开(公告)日：2017-10-26

申请号：US15649051

申请日：2017-07-13

申请人： Renesas Electronics Corporation

发明人： Hiromi Notani ,  Takayuki Fukuoka ,  Takashi Yamaki

IPC分类号： G06F1/26

CPC分类号： G06F1/263

摘要： A semiconductor device having an active mode and a standby mode as operation modes, includes a first power supply line supplied with a first internal power supply voltage from a first external power supply and an internal power supply circuit generating a second internal power supply voltage based on an external power supply voltage from a second external power supply circuit.A second power supply line supplied with said second internal power supply voltage from said internal power supply circuit.

公开(公告)号：US09412459B2

公开(公告)日：2016-08-09

申请号：US14214969

申请日：2014-03-16

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Toshihiro Tanaka ,  Yukiko Umemoto ,  Mitsuru Hiraki ,  Yutaka Shinagawa ,  Masamichi Fujito ,  Kazufumi Suzukawa ,  Hiroyuki Tanikawa ,  Takashi Yamaki ,  Yoshiaki Kamigaki ,  Shinichi Minami ,  Kozo Katayama ,  Nozomu Matsuzaki

IPC分类号： G11C16/26 ,  H01L21/28 ,  H01L27/105 ,  H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  G11C16/24 ,  G11C16/04

CPC分类号： G11C16/26 ,  G11C5/025 ,  G11C8/08 ,  G11C16/04 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  H01L21/28 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/7885 ,  H01L29/792

摘要： A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc

公开(公告)号：US20140189381A1

公开(公告)日：2014-07-03

申请号：US14134537

申请日：2013-12-19

申请人： Renesas Electronics Corporation

发明人： Hiromi Notani ,  Takayuki Fukuoka ,  Takashi Yamaki

IPC分类号： G06F1/26

CPC分类号： G06F1/263

摘要： In an active mode, a VDD line receives an internal power supply voltage from an external regulator. A VDD_RAM line receives an internal power supply voltage from an internal regulator. A PMOS switch includes a first PMOS transistor having a source and an N-type well connected to the VDD line, and a second PMOS transistor having a source and an N-type well connected to the VDD_RAM line and a drain connected to a drain of the first PMOS transistor. The first PMOS transistor is controlled based on a control command from a system control circuit and a voltage of the VDD_RAM line. The second PMOS transistor is controlled based on the control command and a voltage of the VDD line.

摘要翻译： 在有源模式下，VDD线从外部稳压器接收内部电源电压。 VDD_RAM线从内部稳压器接收内部电源电压。 PMOS开关包括具有源极和连接到VDD线的N型阱的第一PMOS晶体管和具有连接到VDD_RAM线的源极和N型阱的第二PMOS晶体管，以及连接到VDD线的漏极的漏极 第一个PMOS晶体管。 基于来自系统控制电路的控制命令和VDD_RAM线的电压来控制第一PMOS晶体管。 基于控制命令和VDD线的电压来控制第二PMOS晶体管。

公开(公告)号：US09727106B2

公开(公告)日：2017-08-08

申请号：US14134537

申请日：2013-12-19

申请人： Renesas Electronics Corporation

发明人： Hiromi Notani ,  Takayuki Fukuoka ,  Takashi Yamaki

IPC分类号： G06F1/26

CPC分类号： G06F1/263

摘要： In an active mode, a VDD line receives an internal power supply voltage from an external regulator. A VDD_RAM line receives an internal power supply voltage from an internal regulator. A PMOS switch includes a first PMOS transistor having a source and an N-type well connected to the VDD line, and a second PMOS transistor having a source and an N-type well connected to the VDD_RAM line and a drain connected to a drain of the first PMOS transistor. The first PMOS transistor is controlled based on a control command from a system control circuit and a voltage of the VDD_RAM line. The second PMOS transistor is controlled based on the control command and a voltage of the VDD line.

公开(公告)号：US08698224B2

公开(公告)日：2014-04-15

申请号：US13867055

申请日：2013-04-20

申请人： Renesas Electronics Corporation ,  Hitachi ULSI Systems Co., Ltd.

发明人： Toshihiro Tanaka ,  Yukiko Umemoto ,  Mitsuru Hiraki ,  Yutaka Shinagawa ,  Masamichi Fujito ,  Kazufumi Suzukawa ,  Hiroyuki Tanikawa ,  Takashi Yamaki ,  Yoshiaki Kamigaki ,  Shinichi Minami ,  Kozo Katayama ,  Nozomu Matsuzaki

IPC分类号： H01L29/788

CPC分类号： G11C16/26 ,  G11C5/025 ,  G11C8/08 ,  G11C16/04 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  H01L21/28 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/7885 ,  H01L29/792

摘要： A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc

摘要翻译： 半导体器件包括多个非易失性存储单元（1）。 每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。 第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。 第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。 第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。 假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc

公开(公告)号：US10650883B2

公开(公告)日：2020-05-12

申请号：US16190557

申请日：2018-11-14

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Takashi Yamaki

IPC分类号： G11C5/02 ,  G11C11/419 ,  G11C11/413 ,  G11C7/22 ,  G11C5/14 ,  G06F1/26 ,  G06F3/06 ,  G11C11/418 ,  G11C11/417

摘要： In a semiconductor device, memory modules each having a low power consumption mode that is enabled and disabled by a control signal belong to a memory block. A transmission path of the control signal is provided such that the control signal is inputted in parallel to the memory module via an inside-of-module path, and such that the control signal is outputted by a particular memory module of the memory modules via the inside-of-module path to a downstream outside-of-module path. The particular memory module in the memory block is selected such that it has a greater storage capacity than the other memory modules belonging to this same memory block have.

公开(公告)号：US10354735B2

公开(公告)日：2019-07-16

申请号：US16116893

申请日：2018-08-29

申请人： Renesas Electronics Corporation

发明人： Toshihiro Tanaka ,  Yukiko Umemoto ,  Mitsuru Hiraki ,  Yutaka Shinagawa ,  Masamichi Fujito ,  Kazufumi Suzukawa ,  Hiroyuki Tanikawa ,  Takashi Yamaki ,  Yoshiaki Kamigaki ,  Shinichi Minami ,  Kozo Katayama ,  Nozomu Matsuzaki

IPC分类号： G11C16/26 ,  G11C16/04 ,  H01L21/28 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  G11C16/24 ,  G11C5/02 ,  G11C8/08 ,  G11C16/08 ,  G11C16/30

摘要： A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc