公开(公告)号：US10263522B2

公开(公告)日：2019-04-16

申请号：US15985155

申请日：2018-05-21

申请人： Renesas Electronics Corporation

发明人： Daisuke Kondo ,  Koji Tateno ,  Yumi Kishita ,  Tomoaki Uno

IPC分类号： H02M3/158 ,  H03K17/06 ,  H02M1/08 ,  H02M1/00

摘要： A semiconductor integrated circuit device includes a first voltage terminal, a second voltage terminal, an output terminal, a high-side MOSFET connected between the first voltage terminal and the output terminal, a low-side MOSFET connected between the output terminal and the second voltage terminal and having first and second gate electrodes, a drive circuit that complementally switches on and off the high-side MOSFET and low-side MOSFET, and a second gate electrode control circuit that generates a second gate control signal supplied to the second gate electrode of the low-side MOSFET. The second gate electrode control circuit has a voltage generating circuit that supplies a negative voltage negative in polarity relative to a voltage at the source of the low-side MOSFET, to the second gate electrode of the low-side MOSFET.

公开(公告)号：US10003262B2

公开(公告)日：2018-06-19

申请号：US15630854

申请日：2017-06-22

申请人： Renesas Electronics Corporation

发明人： Daisuke Kondo ,  Koji Tateno ,  Yumi Kishita ,  Tomoaki Uno

IPC分类号： H02M3/158 ,  H02M1/08 ,  H03K17/06 ,  H02M1/00

CPC分类号： H02M3/158 ,  H01L2224/40245 ,  H01L2224/48137 ,  H01L2924/00014 ,  H01L2924/13091 ,  H02M1/08 ,  H02M3/1588 ,  H02M2001/0009 ,  H02M2001/0032 ,  H02M2001/0054 ,  H03K17/063 ,  H03K2217/0036 ,  Y02B70/1466 ,  Y02B70/16 ,  H01L2224/37099 ,  H01L2924/00

摘要： A semiconductor integrated circuit device includes a first voltage terminal, a second voltage terminal, an output terminal, a high-side MOSFET connected between the first voltage terminal and the output terminal, a low-side MOSFET connected between the output terminal and the second voltage terminal and having first and second gate electrodes, a drive circuit that complementally switches on and off the high-side MOSFET and low-side MOSFET, and a second gate electrode control circuit that generates a second gate control signal supplied to the second gate electrode of the low-side MOSFET. The second gate electrode control circuit has a voltage generating circuit that supplies a negative voltage negative in polarity relative to a voltage at the source of the low-side MOSFET, to the second gate electrode of the low-side MOSFET.

公开(公告)号：US20170288549A1

公开(公告)日：2017-10-05

申请号：US15630854

申请日：2017-06-22

申请人： Renesas Electronics Corporation

发明人： Daisuke Kondo ,  Koji Tateno ,  Yumi Kishita ,  Tomoaki Uno

IPC分类号： H02M3/158 ,  H03K17/06 ,  H02M1/08

CPC分类号： H02M3/158 ,  H01L2224/40245 ,  H01L2224/48137 ,  H01L2924/00014 ,  H02M1/08 ,  H02M3/1588 ,  H02M2001/0009 ,  H02M2001/0032 ,  H02M2001/0054 ,  H03K17/063 ,  H03K2217/0036 ,  Y02B70/1466 ,  Y02B70/16 ,  H01L2224/37099

摘要： A semiconductor integrated circuit device includes a first voltage terminal, a second voltage terminal, an output terminal, a high-side MOSFET connected between the first voltage terminal and the output terminal, a low-side MOSFET connected between the output terminal and the second voltage terminal and having first and second gate electrodes, a drive circuit that complementally switches on and off the high-side MOSFET and low-side MOSFET, and a second gate electrode control circuit that generates a second gate control signal supplied to the second gate electrode of the low-side MOSFET. The second gate electrode control circuit has a voltage generating circuit that supplies a negative voltage negative in polarity relative to a voltage at the source of the low-side MOSFET, to the second gate electrode of the low-side MOSFET.

公开(公告)号：US09704844B2

公开(公告)日：2017-07-11

申请号：US15133032

申请日：2016-04-19

申请人： Renesas Electronics Corporation

发明人： Katsuhiko Funatsu ,  Tomoaki Uno ,  Toru Ueguri ,  Yukihiro Sato

IPC分类号： H01L23/495 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L21/683 ,  H01L21/78 ,  H01L25/18

CPC分类号： H01L25/50 ,  H01L21/4835 ,  H01L21/4839 ,  H01L21/56 ,  H01L21/561 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/495 ,  H01L23/49503 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L24/83 ,  H01L24/97 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/29139 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/84801 ,  H01L2224/92247 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： To improve the reliability in applying a tape to the rear surface of a substrate while securing the heat resistance of the tape applied to the rear surface of the substrate. There is a gap between a bottom surface of a ditch provided in a support member and an upper surface of a driver IC chip. On the other hand, the upper surface side of a lead frame is supported by the support member so that the bottom surface of the ditch contacts the upper surface of a Low-MOS clip mounted over a Low-MOS chip. Thus, even in a state where the driver IC chip and the Low-MOS chip are mounted on the upper surface side of the lead frame, the tape can be reliably applied to the rear surface of the lead frame (in particular, to the rear surface of the product region).

公开(公告)号：US09478483B2

公开(公告)日：2016-10-25

申请号：US13764336

申请日：2013-02-11

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Yukihiro Sato ,  Tomoaki Uno

IPC分类号： H01L23/492 ,  H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H02M7/00

CPC分类号： H01L23/492 ,  H01L23/3107 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/05 ,  H01L24/33 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/91 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/37599 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/4847 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/49111 ,  H01L2224/49112 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/85439 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/351 ,  H02M7/003 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2924/00 ,  H01L2924/00012

摘要： The reliability of a semiconductor device is improved. A package of a semiconductor device internally includes a first semiconductor chip and a second semiconductor chip in which power MOS•FETs are formed and a third semiconductor chip in which a control circuit controlling the first and second semiconductor chips is formed. The first to third semiconductor chips are mounted on die pads respectively. Source electrode bonding pads of the first semiconductor chip on a high side are electrically connected with a first die pad of the die pads via a metal plate. On a top surface of the die pad 7D2, a plated layer formed in a region where the second semiconductor chip is mounted, and another plated layer formed in a region where the metal plate is joined are provided and the plated layers are separated each other with a region where no plated layer is formed in between.

摘要翻译： 提高了半导体器件的可靠性。 半导体器件的封装在内部包括形成功率MOS•FET的第一半导体芯片和第二半导体芯片，以及形成控制第一和第二半导体芯片的控制电路的第三半导体芯片。 第一至第三半导体芯片分别安装在芯片焊盘上。 第一半导体芯片的高侧的源电极接合焊盘通过金属板与管芯焊盘的第一管芯焊盘电连接。 在芯片焊盘7D2的顶面设置有形成在安装有第二半导体芯片的区域中的镀层和形成在金属板接合的区域中的另一个镀层，并且将镀层彼此分离，并且用 在其间不形成镀层的区域。

公开(公告)号：US09362238B2

公开(公告)日：2016-06-07

申请号：US14919597

申请日：2015-10-21

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Katsuhiko Funatsu ,  Yukihiro Sato ,  Yuichi Yato ,  Tomoaki Uno

IPC分类号： H01L21/44 ,  H01L23/00 ,  H01L21/78 ,  H01L21/56 ,  H01L21/48

CPC分类号： H01L23/564 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/34 ,  H01L24/36 ,  H01L24/40 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A semiconductor device includes a first chip mounting portion, a first semiconductor chip arranged over the first chip mounting portion, a first pad formed in a surface of the first semiconductor chip, a first lead which serves as an external coupling terminal, a first conductive member which electrically couples the first pad and the first lead, and a sealing body which seals a part of the first chip mounting portion, the first semiconductor chip, a part of the first lead, and the first conductive member. The first conductive member includes a first plate-like portion, and a first support portion formed integrally with the first plate-like portion. An end of the first support portion is exposed from the sealing body, and the first support portion is formed with a first bent portion.

公开(公告)号：US09236321B2

公开(公告)日：2016-01-12

申请号：US13754245

申请日：2013-01-30

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Tomoaki Uno ,  Tetsuya Kawashima

IPC分类号： H01L23/48 ,  H01L23/34 ,  H01L21/50 ,  H01L21/8234 ,  H01L27/088 ,  H01L23/00

CPC分类号： H01L21/50 ,  H01L21/823475 ,  H01L23/34 ,  H01L24/34 ,  H01L24/37 ,  H01L24/40 ,  H01L27/088 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/01015 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A conventional semiconductor device used for a power supply circuit such as a DC/DC converter has problems of heat dissipation and downsizing, in particular has the problems of heat dissipation and others in the event of downsizing.A semiconductor device has a structure formed by covering a principal surface of a semiconductor chip having the principal surface and a plurality of MIS type FETs formed over the principal surface with a plurality of metal plate wires having pectinate shapes; allocating the pectinate parts alternately in a planar view over the principal surface; and further electrically coupling the plural metal plate wires to a plurality of terminals.

摘要翻译： 用于诸如DC / DC转换器的电源电路的常规半导体器件具有散热和小型化的问题，特别是在尺寸减小的情况下具有散热等问题。 半导体器件具有通过覆盖具有主表面的半导体芯片的主表面和在主表面上形成的多个MIS型FET的多个具有果胶形状的金属板线而形成的结构; 在主表面上的平面视图中交替地分配果胶部分; 并且还将多个金属板电线进一步电耦合到多个端子。

公开(公告)号：US20150256072A1

公开(公告)日：2015-09-10

申请号：US14418934

申请日：2014-01-31

申请人： Renesas Electronics Corporation

发明人： Daisuke Kondo ,  Koji Tateno ,  Yumi Kishita ,  Tomoaki Uno

IPC分类号： H02M3/158

CPC分类号： H02M3/158 ,  H01L2224/40245 ,  H01L2224/48137 ,  H01L2924/00014 ,  H02M1/08 ,  H02M3/1588 ,  H02M2001/0009 ,  H02M2001/0032 ,  H02M2001/0054 ,  H03K17/063 ,  H03K2217/0036 ,  Y02B70/1466 ,  Y02B70/16 ,  H01L2224/37099

摘要： A semiconductor integrated circuit device includes a first voltage terminal, a second voltage terminal, an output terminal, a high-side MOSFET connected between the first voltage terminal and the output terminal, a low-side MOSFET connected between the output terminal and the second voltage terminal and having first and second gate electrodes, a drive circuit that complementally switches on and off the high-side MOSFET and low-side MOSFET, and a second gate electrode control circuit that generates a second gate control signal supplied to the second gate electrode of the low-side MOSFET. The second gate electrode control circuit has a voltage generating circuit that supplies a negative voltage negative in polarity relative to a voltage at the source of the low-side MOSFET, to the second gate electrode of the low-side MOSFET.

摘要翻译： 一种半导体集成电路器件，包括：第一电压端子，第二电压端子，输出端子，连接在第一电压端子和输出端子之间的高侧MOSFET，连接在输出端子与第二电压之间的低端MOSFET 并具有第一和第二栅电极，互补地接通和断开高侧MOSFET和低侧MOSFET的驱动电路，以及产生提供给第二栅电极的第二栅极控制信号的第二栅电极控制电路 低端MOSFET。 第二栅电极控制电路具有电压产生电路，其将相对于低侧MOSFET的源极处的极性的负电压提供给低侧MOSFET的第二栅电极。

公开(公告)号：US09029995B2

公开(公告)日：2015-05-12

申请号：US14037489

申请日：2013-09-26

申请人： Renesas Electronics Corporation

发明人： Katsuhiko Funatsu ,  Tomoaki Uno ,  Toru Ueguri ,  Yasushi Takahashi

IPC分类号： H01L23/48 ,  H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L23/49513 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/4924 ,  H01L23/495 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/34 ,  H01L24/37 ,  H01L24/38 ,  H01L24/40 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/97 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： To enhance the reliability of connection between a semiconductor chip and a metal plate by ensuring sufficiently the thickness of a conductive material interposed between the semiconductor chip and the metal plate. A lead frame is arranged over a jig and a clip frame is arranged over protruding portions provided on the jig. In this state, a heating process (reflow) is performed. In this case, high melting point solders filling first spaces are melted in a state in which the first space is formed between a High-MOS chip and a High-MOS clip and the first space is formed between a Low-MOS chip and a Low-MOS clip. At this time, even when the high melting point solder is melted in the first space, the size (in particular, the height) of the first space does not change and the first space is maintained.

摘要翻译： 通过确保插入在半导体芯片和金属板之间的导电材料的厚度充分地提高半导体芯片和金属板之间的连接的可靠性。 引线框架布置在夹具上方，并且夹具框架布置在设置在夹具上的突出部分上。 在该状态下，进行加热处理（回流）。 在这种情况下，填充第一空间的高熔点焊料在高MOS芯片和高MOS夹之间形成第一空间的状态下熔化，并且第一空间形成在低MOS芯片与低电压 -MOS剪辑。 此时，即使高熔点焊料在第一空间中熔化，第一空间的尺寸（特别是高度）也不变，保持第一空间。

公开(公告)号：US10204899B2

公开(公告)日：2019-02-12

申请号：US15700679

申请日：2017-09-11

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Masaki Shiraishi ,  Tomoaki Uno ,  Nobuyoshi Matsuura

IPC分类号： H01L27/06 ,  H01L23/31 ,  H01L23/495 ,  H01L23/00 ,  H01L29/78 ,  H02M7/00 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/66 ,  H02M3/155 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/872

摘要： In a non-insulated DC-DC converter having a circuit in which a power MOS⋅FET high-side switch and a power MOS⋅FET low-side switch are connected in series, the power MOS⋅FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS⋅FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS⋅FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.