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公开(公告)号：US07298667B2
公开(公告)日：2007-11-20
申请号：US11202314
申请日：2005-08-12
申请人： Reum Oh , Sang-bo Lee , Moo-sung Chae , Ho-young Song
发明人： Reum Oh , Sang-bo Lee , Moo-sung Chae , Ho-young Song
IPC分类号： G11C8/00
CPC分类号： G11C29/023 , G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C11/401 , G11C29/02 , G11C29/028 , G11C29/50012 , G11C2207/2254
摘要： In one embodiment, a latency circuit generates the latency signal based on CAS latency information and read information. For example, the latency circuit may include a clock signal generating circuit generating a plurality of transfer signals and generating a plurality of sampling clock signals based on and corresponding to the plurality of transfer signals such that a timing relationship is created between the transfer signals and the sampling clock signals. The latency circuit may further include a latency signal generator selectively storing the read information based on the sampling clock signals, and selectively outputting the stored read information as the latency signal based on the transfer signals. The latency signal generator may also delay the read information such that the delayed, read information is stored based on the sampling clock signals.
摘要翻译： 在一个实施例中，延迟电路基于CAS等待时间信息和读取信息生成等待时间信号。 例如，等待时间电路可以包括产生多个传送信号的时钟信号发生电路，并且基于并对应于多个传送信号产生多个采样时钟信号，使得在传送信号和传输信号之间产生定时关系 采样时钟信号。 延迟电路还可以包括等待时间信号发生器，其基于采样时钟信号选择性地存储读取的信息，并且基于传送信号选择性地输出存储的读取信息作为等待时间信号。 等待时间信号发生器还可以延迟读取信息，使得基于采样时钟信号来存储延迟读取信息。
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公开(公告)号：US20060077751A1
公开(公告)日：2006-04-13
申请号：US11202314
申请日：2005-08-12
申请人： Reum Oh , Sang-bo Lee , Moo-sung Chae , Ho-young Song
发明人： Reum Oh , Sang-bo Lee , Moo-sung Chae , Ho-young Song
IPC分类号： G11C8/02
CPC分类号： G11C29/023 , G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C11/401 , G11C29/02 , G11C29/028 , G11C29/50012 , G11C2207/2254
摘要： In one embodiment, a latency circuit generates the latency signal based on CAS latency information and read information. For example, the latency circuit may include a clock signal generating circuit generating a plurality of transfer signals and generating a plurality of sampling clock signals based on and corresponding to the plurality of transfer signals such that a timing relationship is created between the transfer signals and the sampling clock signals. The latency circuit may further include a latency signal generator selectively storing the read information based on the sampling clock signals, and selectively outputting the stored read information as the latency signal based on the transfer signals. The latency signal generator may also delay the read information such that the delayed, read information is stored based on the sampling clock signals.
摘要翻译： 在一个实施例中，延迟电路基于CAS等待时间信息和读取信息生成等待时间信号。 例如，等待时间电路可以包括产生多个传送信号的时钟信号发生电路，并且基于并对应于多个传送信号产生多个采样时钟信号，使得在传送信号和传输信号之间产生定时关系 采样时钟信号。 延迟电路还可以包括等待时间信号发生器，其基于采样时钟信号选择性地存储读取的信息，并且基于传送信号选择性地输出存储的读取信息作为等待时间信号。 等待时间信号发生器还可以延迟读取信息，使得基于采样时钟信号来存储延迟读取信息。
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公开(公告)号：US06944091B2
公开(公告)日：2005-09-13
申请号：US10727579
申请日：2003-12-05
申请人： Sang-bo Lee , Ho-young Song
发明人： Sang-bo Lee , Ho-young Song
IPC分类号： G11C11/407 , G11C7/10 , G11C7/22 , G11C8/00
CPC分类号： G11C7/1066 , G11C7/1045 , G11C7/1051 , G11C7/22 , G11C7/222 , G11C2207/2281
摘要： The memory device includes a memory cell array, and an output buffer receiving data addressed from the memory cell array and outputting the data based on a latency signal. A latency circuit selectively associates at least one transfer signal with at least one sampling signal based on CAS latency information to create a desired timing relationship between the associated sampling and transfer signals. The latency circuit stores read information in accordance with at least one of the sampling signals, and generates a latency signal based on the transfer signal associated with the sampling signal used in storing the read information.
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公开(公告)号：US20050254337A1
公开(公告)日：2005-11-17
申请号：US11188708
申请日：2005-07-26
申请人： Sang-bo Lee , Ho-young Song
发明人： Sang-bo Lee , Ho-young Song
IPC分类号： G11C11/407 , G11C7/10 , G11C7/22 , G11C8/00
CPC分类号： G11C7/1066 , G11C7/1045 , G11C7/1051 , G11C7/22 , G11C7/222 , G11C2207/2281
摘要： The memory device includes a memory cell array, and an output buffer receiving data addressed from the memory cell array and outputting the data based on a latency signal. A latency circuit selectively associates at least one transfer signal with at least one sampling signal based on CAS latency information to create a desired timing relationship between the associated sampling and transfer signals. The latency circuit stores read information in accordance with at least one of the sampling signals, and generates a latency signal based on the transfer signal associated with the sampling signal used in storing the read information.
摘要翻译： 存储器件包括存储器单元阵列和从存储单元阵列寻址的数据的输出缓冲器，并且基于等待时间信号输出数据。 延迟电路基于CAS等待时间信息选择性地将至少一个传送信号与至少一个采样信号相关联，以在相关联的采样和传送信号之间产生期望的时序关系。 延迟电路根据至少一个采样信号存储读取信息，并且基于与用于存储读取的信息的采样信号相关联的传送信号产生等待时间信号。
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公开(公告)号：US07065003B2
公开(公告)日：2006-06-20
申请号：US11188708
申请日：2005-07-26
申请人： Sang-bo Lee , Ho-young Song
发明人： Sang-bo Lee , Ho-young Song
IPC分类号： G11C8/00
CPC分类号： G11C7/1066 , G11C7/1045 , G11C7/1051 , G11C7/22 , G11C7/222 , G11C2207/2281
摘要： The memory device includes a memory cell array, and an output buffer receiving data addressed from the memory cell array and outputting the data based on a latency signal. A latency circuit selectively associates at least one transfer signal with at least one sampling signal based on CAS latency information to create a desired timing relationship between the associated sampling and transfer signals. The latency circuit stores read information in accordance with at least one of the sampling signals, and generates a latency signal based on the transfer signal associated with the sampling signal used in storing the read information.
摘要翻译： 存储器件包括存储器单元阵列和从存储单元阵列寻址的数据的输出缓冲器，并且基于等待时间信号输出数据。 延迟电路基于CAS等待时间信息选择性地将至少一个传送信号与至少一个采样信号相关联，以在相关联的采样和传输信号之间产生期望的时序关系。 延迟电路根据至少一个采样信号存储读取信息，并且基于与用于存储读取的信息的采样信号相关联的传送信号产生等待时间信号。
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公开(公告)号：US20110208988A1
公开(公告)日：2011-08-25
申请号：US13064961
申请日：2011-04-28
申请人： Hyun-Jin Kim , Ho-young Song , Seong-Jin Jang , Youn-sik Park
发明人： Hyun-Jin Kim , Ho-young Song , Seong-Jin Jang , Youn-sik Park
IPC分类号： G06F1/04
摘要： A latency signal generator and method thereof are provided. The example latency signal generator may include a sampling clock signal generator adjusting a plurality of initial sampling clock signals based on a received clock signal to generate a plurality of adjusted sampling clock signals, a latch enable signal supply unit adjusting a plurality of initial latch enable signals based on a given one of the plurality of initial sampling clock signals to generate a plurality of adjusted latch enable signals and a latch unit including a plurality of latency latches, each of the plurality of latency latches selectively latching a given internal read command based on one of the plurality of adjusted sampling clock signals and one of the plurality of adjusted latch enable signals.
摘要翻译： 提供了一种等待时间信号发生器及其方法。 示例性延迟信号发生器可以包括采样时钟信号发生器，其基于所接收的时钟信号来调整多个初始采样时钟信号，以产生多个经调整的采样时钟信号;锁存使能信号供应单元，调整多个初始锁存使能信号 基于所述多个初始采样时钟信号中的给定一个以产生多个调整的锁存使能信号，以及包括多个延迟锁存器的锁存单元，所述多个延迟锁存器中的每一个基于一个等待锁存器选择性地锁存给定的内部读取命令 多个经调整的采样时钟信号中的一个和多个调整的锁存使能信号中的一个。
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公开(公告)号：US07499370B2
公开(公告)日：2009-03-03
申请号：US11850754
申请日：2007-09-06
申请人： Hyun-jin Kim , Ho-young Song , Youn-sik Park , Seong-jin Jang
发明人： Hyun-jin Kim , Ho-young Song , Youn-sik Park , Seong-jin Jang
IPC分类号： G11C8/00
CPC分类号： G11C7/1072 , G11C7/1057 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4093
摘要： A synchronous semiconductor memory device includes an output control signal generator, which generates an output control signal corresponding to a signal obtained by delaying a read information signal in response to a delay internal clock signal obtained by dividing an internal clock signal by n, first and second sampling signals obtained by delaying the internal clock signal, a first output control clock signal obtained by dividing the internal clock signal by n, and a column address strobe (CAS) latency signal. The synchronous semiconductor memory device also includes a data output buffer, which outputs data by buffering internal data in response to the output control signal and the first output control clock signal.
摘要翻译： 一个同步半导体存储器件包括一个输出控制信号发生器，它产生一个输出控制信号，该输出控制信号对应于通过将内部时钟信号除以n而获得的延迟内部时钟信号延迟读取信息信号获得的信号，第一和第二 通过延迟内部时钟信号获得的采样信号，通过将内部时钟信号除以n获得的第一输出控制时钟信号和列地址选通（CAS）等待时间信号。 同步半导体存储器件还包括数据输出缓冲器，其通过响应于输出控制信号和第一输出控制时钟信号缓冲内部数据而输出数据。
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公开(公告)号：US20080056019A1
公开(公告)日：2008-03-06
申请号：US11896788
申请日：2007-09-06
申请人： Hyun-jin Kim , Ho-young Song , Seong-jin Jang , Youn-sik Park
发明人： Hyun-jin Kim , Ho-young Song , Seong-jin Jang , Youn-sik Park
摘要： A latency signal generator and method thereof are provided. The example latency signal generator may include a sampling clock signal generator adjusting a plurality of initial sampling clock signals based on a received clock signal to generate a plurality of adjusted sampling clock signals, a latch enable signal supply unit adjusting a plurality of initial latch enable signals based on a given one of the plurality of initial sampling clock signals to generate a plurality of adjusted latch enable signals and a latch unit including a plurality of latency latches, each of the plurality of latency latches selectively latching a given internal read command based on one of the plurality of adjusted sampling clock signals and one of the plurality of adjusted latch enable signals.
摘要翻译： 提供了一种等待时间信号发生器及其方法。 示例性延迟信号发生器可以包括采样时钟信号发生器，其基于所接收的时钟信号来调整多个初始采样时钟信号，以产生多个经调整的采样时钟信号;锁存使能信号供应单元，调整多个初始锁存使能信号 基于所述多个初始采样时钟信号中的给定一个以产生多个调整的锁存使能信号，以及包括多个延迟锁存器的锁存单元，所述多个延迟锁存器中的每一个基于一个等待锁存器选择性地锁存给定的内部读取命令 多个经调整的采样时钟信号中的一个和多个调整的锁存使能信号中的一个。
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公开(公告)号：US20160048425A1
公开(公告)日：2016-02-18
申请号：US14722823
申请日：2015-05-27
申请人： Hyun-joong Kim , Soo-hyeong Kim , Sang-hoon Shin , Ju-yun Jung , Ho-young Song , Kyo-min Sohn , Hae-suk Lee , Bu-il Jung , Han-vit Jeong
发明人： Hyun-joong Kim , Soo-hyeong Kim , Sang-hoon Shin , Ju-yun Jung , Ho-young Song , Kyo-min Sohn , Hae-suk Lee , Bu-il Jung , Han-vit Jeong
CPC分类号： G11C29/52 , G06F11/1048 , G11C2029/0411
摘要： A memory device including: an error correction code (ECC) cell array; an ECC engine configured to receive write data to be written to a memory cell array and generate internal parity bits for the write data; and an ECC select unit configured to receive the internal parity bits and external parity bits and, in response to a first level of a control signal, store the internal parity bits in the ECC cell array and, in response to a second level of the control signal store the external parity bits in the ECC cell array.
摘要翻译： 一种存储器件，包括：纠错码（ECC）单元阵列; ECC引擎，被配置为接收要写入存储单元阵列的写入数据，并为写入数据生成内部奇偶校验位; 以及ECC选择单元，被配置为接收内部奇偶校验位和外部奇偶校验位，并且响应于控制信号的第一电平将内部奇偶校验位存储在ECC单元阵列中，并且响应于第二级别的控制 信号存储ECC单元阵列中的外部奇偶校验位。
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公开(公告)号：US07958382B2
公开(公告)日：2011-06-07
申请号：US11896788
申请日：2007-09-06
申请人： Hyun-jin Kim , Ho-young Song , Seong-jin Jang , Youn-sik Park
发明人： Hyun-jin Kim , Ho-young Song , Seong-jin Jang , Youn-sik Park
摘要： A latency signal generator and method thereof are provided. The example latency signal generator may include a sampling clock signal generator adjusting a plurality of initial sampling clock signals based on a received clock signal to generate a plurality of adjusted sampling clock signals, a latch enable signal supply unit adjusting a plurality of initial latch enable signals based on a given one of the plurality of initial sampling clock signals to generate a plurality of adjusted latch enable signals and a latch unit including a plurality of latency latches, each of the plurality of latency latches selectively latching a given internal read command based on one of the plurality of adjusted sampling clock signals and one of the plurality of adjusted latch enable signals.
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