-
1.发明授权Method for supporting multiple libraries characterized at different process, voltage and temperature points 失效支持以不同过程，电压和温度点为特征的多个库的方法公开(公告)号：US08549452B2
公开(公告)日：2013-10-01
申请号：US12774766
申请日：2010-05-06
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5031 , G06F2217/08 , G06F2217/78 , G06F2217/82 , G06F2217/84
摘要： A method for accurately performing a timing, power, and noise analysis by pre-processing the characterization points of the available libraries, storing time consuming parts of the analysis and utilizing the pre-processed information during active runs to calculate the attributes at a desired PVT point. The PVT space is preferably sub-divided into triangular or rectangular regions, preferably obtained using Delaunay triangulation. In one embodiment, the invention performs an up-front pre-processing step on the characterized libraries to compute the static portion of the interpolation function that is independent of the specific instance; and a coefficient matrix that allows for interpolation of specific instances.
摘要翻译： 一种用于通过预处理可用库的表征点来准确地执行定时，功率和噪声分析的方法，存储分析的时间消耗部分并且在主动运行期间利用预处理信息来计算期望PVT处的属性 点。 PVT空间优选地分为三角形或矩形区域，优选地使用Delaunay三角测量法获得。 在一个实施例中，本发明对特征库执行前期预处理步骤，以计算独立于特定实例的内插函数的静态部分; 以及允许特定实例的插值的系数矩阵。
-
2.发明申请公开(公告)号：US20110276933A1
公开(公告)日：2011-11-10
申请号：US12774766
申请日：2010-05-06
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5031 , G06F2217/08 , G06F2217/78 , G06F2217/82 , G06F2217/84
摘要： A method for accurately performing a timing, power, and noise analysis by pre-processing the characterization points of the available libraries, storing time consuming parts of the analysis and utilizing the pre-processed information during active runs to calculate the attributes at a desired PVT point. The PVT space is preferably sub-divided into triangular or rectangular regions, preferably obtained using Delaunay triangulation. In one embodiment, the invention performs an up-front pre-processing step on the characterized libraries to compute the static portion of the interpolation function that is independent of the specific instance; and a coefficient matrix that allows for interpolation of specific instances.
摘要翻译： 一种用于通过预处理可用库的表征点来准确地执行定时，功率和噪声分析的方法，存储分析的时间消耗部分并且在主动运行期间利用预处理信息来计算期望PVT处的属性 点。 PVT空间优选地分为三角形或矩形区域，优选地使用Delaunay三角测量法获得。 在一个实施例中，本发明对特征库执行前期预处理步骤，以计算独立于特定实例的内插函数的静态部分; 以及允许特定实例的插值的系数矩阵。
-
3.发明授权Method for improving static timing analysis and optimizing circuits using reverse merge 失效改进静态时序分析和使用反向合并优化电路的方法公开(公告)号：US08776004B2
公开(公告)日：2014-07-08
申请号：US13006450
申请日：2011-01-14
申请人： Frank Borkam , Hemlata Gupta , David J. Hathaway , Kerim Kalafala , Vasant Rao , Alex Rubin
发明人： Frank Borkam , Hemlata Gupta , David J. Hathaway , Kerim Kalafala , Vasant Rao , Alex Rubin
CPC分类号： G06F17/5031 , G06F2217/84
摘要： Determining static timing analysis margin on non-controlling inputs of clock shaping and other digital circuits using reverse merge timing includes: selecting one or more circuits within the logic design having a plurality of inputs and using reverse merge; identifying a controlling input of the selected circuit from among this plurality of inputs; and determining for at least one non-controlling input of the circuit, a timing value that may be used to drive design optimization based on the difference between arrival times of the controlling and non-controlling inputs.
摘要翻译： 使用反向合并定时确定时钟整形和其他数字电路的非控制输入端的静态时序分析余量包括：在逻辑设计中选择一个或多个具有多个输入并使用反向合并的电路; 从所述多个输入中识别所选择的电路的控制输入; 以及为所述电路的至少一个非控制输入确定可基于所述控制和非控制输入的到达时间之间的差异来驱动设计优化的定时值。
-
4.发明申请Method for Improving Static Timing Analysis and Optimizing Circuits Using Reverse Merge 失效使用反向合并改进静态时序分析和优化电路的方法公开(公告)号：US20120185810A1
公开(公告)日：2012-07-19
申请号：US13006450
申请日：2011-01-14
申请人： Frank Borkam , Hemlata Gupta , David J. Hathaway , Kerim Kalafala , Vasant Rao , Alex Rubin
发明人： Frank Borkam , Hemlata Gupta , David J. Hathaway , Kerim Kalafala , Vasant Rao , Alex Rubin
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： Determining static timing analysis margin on non-controlling inputs of clock shaping and other digital circuits using reverse merge timing includes: selecting one or more circuits within the logic design having a plurality of inputs and using reverse merge; identifying a controlling input of the selected circuit from among this plurality of inputs; and determining for at least one non-controlling input of the circuit, a timing value that may be used to drive design optimization based on the difference between arrival times of the controlling and non-controlling inputs.
摘要翻译： 使用反向合并定时确定时钟整形和其他数字电路的非控制输入端的静态时序分析余量包括：在逻辑设计中选择一个或多个具有多个输入并使用反向合并的电路; 从所述多个输入中识别所选择的电路的控制输入; 以及为所述电路的至少一个非控制输入确定可基于所述控制和非控制输入的到达时间之间的差异来驱动设计优化的定时值。
-
5.发明授权Method for efficiently checkpointing and restarting static timing analysis of an integrated circuit chip 有权用于有效地检查和重新启动集成电路芯片的静态时序分析的方法公开(公告)号：US08056038B2
公开(公告)日：2011-11-08
申请号：US12354360
申请日：2009-01-15
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method for loading checkpoint timing in an environment where the boundary arrival times, slews, required arrival times, or loads differ from the checkpoint run. A timing checkpoint file generated for one or more hierarchical modules, during which each input is assigned a unique phase tag. The association of unique phase tags allows subsequent restart analyses to efficiently adjust the checkpoint timing in relation to the restart timing environment. In the restart run, one or more such checkpoint files is read, during which an initial propagation of arrival, required arrivals and slew times are performed, followed by a local re-update based on adjusted arrival times and the required arrival times. Finally, if multiple hierarchical modules are updated, a global recalculation of timing values is performed based on a slack change threshold in order to determine whether any new timing failures have been introduced.
摘要翻译： 在边界到达时间，转数，所需到达时间或负载与检查点运行不同的环境中加载检查点定时的方法。 为一个或多个分层模块生成的定时检查点文件，在此期间为每个输入分配唯一的相位标签。 独特相位标签的关联允许随后的重新启动分析以有效地调整与重启定时环境相关的检查点定时。 在重新启动运行中，读取一个或多个这样的检查点文件，在此期间，执行到达的初始传播，所需到达和转换时间，然后基于调整的到达时间和所需的到达时间进行本地重新更新。 最后，如果更新了多个分级模块，则基于松弛变化阈值执行定时值的全局重新计算，以便确定是否引入了任何新的定时故障。
-
6.发明申请Method For Efficiently Checkpointing And Restarting Static Timing Analysis Of An Integrated Circuit Chip 有权有效地检查和重新启动集成电路芯片的静态时序分析的方法公开(公告)号：US20100180244A1
公开(公告)日：2010-07-15
申请号：US12354360
申请日：2009-01-15
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method for loading checkpoint timing in an environment where the boundary arrival times, slews, required arrival times, or loads differ from the checkpoint run. A timing checkpoint file generated for one or more hierarchical modules, during which each input is assigned a unique phase tag. The association of unique phase tags allows subsequent restart analyses to efficiently adjust the checkpoint timing in relation to the restart timing environment. In the restart run, one or more such checkpoint files is read, during which an initial propagation of arrival, required arrivals and slew times are performed, followed by a local re-update based on adjusted arrival times and the required arrival times. Finally, if multiple hierarchical modules are updated, a global recalculation of timing values is performed based on a slack change threshold in order to determine whether any new timing failures have been introduced.
摘要翻译： 在边界到达时间，转数，所需到达时间或负载与检查点运行不同的环境中加载检查点定时的方法。 为一个或多个分层模块生成的定时检查点文件，在此期间为每个输入分配唯一的相位标签。 独特相位标签的关联允许随后的重新启动分析以有效地调整与重启定时环境相关的检查点定时。 在重新启动运行中，读取一个或多个这样的检查点文件，在此期间，执行到达的初始传播，所需到达和转换时间，然后基于调整的到达时间和所需的到达时间进行本地重新更新。 最后，如果更新了多个分级模块，则基于松弛变化阈值执行定时值的全局重新计算，以便确定是否引入了任何新的定时故障。
-
-
-
-
-
搜索结果
6 条记录 (耗时 0.018 秒)