Hardness tester
    1.
    发明授权
    Hardness tester 有权
    硬度计

    公开(公告)号:US06247356B1

    公开(公告)日:2001-06-19

    申请号:US09281449

    申请日:1999-03-30

    IPC分类号: G01N342

    摘要: A hardness tester having a frame and a rotatable turret movably supported on the frame is provided. A plurality of load cells are fixedly mountable on the turret, and a plurality of indenters are fixedly attachable to the load cells, respectively. A user interface selectively provides signals to a motor to move the turret into contact with a test specimen via one of the indenters to thereby apply a load on the test specimen. The indenters are fixed with respect to the turret and do not move in relation to the turret when the turret is brought down to bear on the test specimen. The load cells measure the load applied to the test specimen. A closed loop control system receives load measurement signals from the load cells and controls movement of the turret, preventing the motor from applying load in excess of a predetermined selectable load amount input by a user via the user interface. The invention preferably includes a plurality of indenter adapters, each attached to respective undersides of the load cells. Each indenter adapter includes a slot into which the indenter is fittable, and least one set screw for adjusting a horizontal location of the indenter.

    摘要翻译: 提供一种具有可移动地支撑在框架上的框架和可旋转转台的硬度计。 多个测力传感器固定地安装在转台上,并且多个压头分别可固定地附接到测力传感器。 用户界面选择性地向马达提供信号,以通过其中一个压头将转台移动到与试样接触,从而在测试样本上施加负载。 压头相对于转台是固定的,并且当转盘被放在试样上时,它们不会相对于转台移动。 称重传感器测量施加到试样上的载荷。 闭环控制系统从负载传感器接收负载测量信号并控制转台的运动,从而防止电动机通过用户界面超过用户输入的预定可选负载量的负载。 本发明优选地包括多个压头适配器,每个连接器连接到称重传感器的相应下侧。 每个压头适配器包括可压入压头的槽,以及用于调节压头水平位置的至少一个固定螺钉。

    Penetration hardness tester
    2.
    发明授权
    Penetration hardness tester 失效
    渗透硬度计

    公开(公告)号:US6142010A

    公开(公告)日:2000-11-07

    申请号:US821461

    申请日:1997-03-21

    IPC分类号: G01N3/00 G01N3/42

    CPC分类号: G01N3/42 G01N2203/0082

    摘要: A hardness tester is disclosed which conducts its hardness test through a penetrator impinging upon the surface of a test specimen. Enhanced accuracy and repeatability is achieved through the use of a closed loop system and directly mounting a load cell to the indentor, connecting a linear displacement transducer directly to the load cell and eliminating an elevating screw in initially positioning and applying load to the specimen to be tested.

    摘要翻译: 公开了一种通过撞击在试样表面上的穿透器来进行其硬度试验的硬度计。 通过使用闭环系统并将称重传感器直接安装在压头上,可以实现提高的精度和重复性,将直线位移传感器直接连接到称重传感器,并消除升降螺钉初始定位并向样品施加载荷 测试。

    Two temperature measuring probe
    3.
    发明授权
    Two temperature measuring probe 失效
    两个温度测量探头

    公开(公告)号:US4842418A

    公开(公告)日:1989-06-27

    申请号:US273614

    申请日:1988-11-17

    申请人: Richard Conti

    发明人: Richard Conti

    摘要: A device for measuring both the phase change temperature of a sample of a molten metal bath and the actual bath temperature by means of a single thermocouple. The device having a chamber defined by a housing such that the housing will be consumed by the molten metal bath after determination of the phase change temperature of the sample within the chamber. After consumption of the housing, the sample remelts into the bath and the thermocouple determines the bath temperature.

    摘要翻译: 一种用于通过单个热电偶测量熔融金属浴样品和实际浴温度的相变温度的装置。 该装置具有由壳体限定的室,使得在确定室内的样品的相变温度之后壳体将被熔融金属浴消耗。 在外壳消耗后,样品再次熔化到浴中,热电偶决定浴温。

    METHOD OF FORMING NITRIDE FILMS WITH HIGH COMPRESSIVE STRESS FOR IMPROVED PFET DEVICE PERFORMANCE
    6.
    发明申请
    METHOD OF FORMING NITRIDE FILMS WITH HIGH COMPRESSIVE STRESS FOR IMPROVED PFET DEVICE PERFORMANCE 有权
    用于改进PFET器件性能的用于形成具有高压应力的氮化物膜的方法

    公开(公告)号:US20080036007A1

    公开(公告)日:2008-02-14

    申请号:US11875217

    申请日:2007-10-19

    IPC分类号: H01L21/8234

    摘要: A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 Å.

    摘要翻译: 提供了一种用于制造其中氮化物层覆盖PFET栅极结构的FET器件的方法,其中氮化物层具有大于约2.8GPa的量级的压缩应力。 这种压应力允许改进PFET中的器件性能。 使用高密度等离子体(HDP)工艺沉积氮化物层,其中衬底设置在供给约50W至约500W范围内的偏置功率的电极上。 偏置功率被表征为高频功率(由13.56MHz的RF发生器提供)。 FET器件还可以包括NFET栅极结构。 在NFET栅极结构上沉积阻挡层,使得氮化物层覆盖阻挡层; 在去除阻挡层之后,氮化物层不与NFET栅极结构接触。 氮化物层的厚度在约300-2000埃的范围内。

    METHOD OF FORMING NITRIDE FILMS WITH HIGH COMPRESSIVE STRESS FOR IMPROVED PFET DEVICE PERFORMANCE
    8.
    发明申请
    METHOD OF FORMING NITRIDE FILMS WITH HIGH COMPRESSIVE STRESS FOR IMPROVED PFET DEVICE PERFORMANCE 失效
    用于改进PFET器件性能的用于形成具有高压应力的氮化物膜的方法

    公开(公告)号:US20070007548A1

    公开(公告)日:2007-01-11

    申请号:US11160705

    申请日:2005-07-06

    摘要: A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 Å.

    摘要翻译: 提供了一种用于制造其中氮化物层覆盖PFET栅极结构的FET器件的方法,其中氮化物层具有大于约2.8GPa的量级的压缩应力。 这种压应力允许改进PFET中的器件性能。 使用高密度等离子体(HDP)工艺沉积氮化物层,其中衬底设置在供给约50W至约500W范围内的偏置功率的电极上。 偏置功率被表征为高频功率(由13.56MHz的RF发生器提供)。 FET器件还可以包括NFET栅极结构。 在NFET栅极结构上沉积阻挡层,使得氮化物层覆盖阻挡层; 在去除阻挡层之后,氮化物层不与NFET栅极结构接触。 氮化物层的厚度在约300-2000埃的范围内。

    BILAYER CAP STRUCTURE INCLUDING HDP/bHDP FILMS FOR CONDUCTIVE METALLIZATION AND METHOD OF MAKING SAME
    9.
    发明申请
    BILAYER CAP STRUCTURE INCLUDING HDP/bHDP FILMS FOR CONDUCTIVE METALLIZATION AND METHOD OF MAKING SAME 失效
    包括用于导电金属化的HDP / bHDP膜的双层盖结构及其制造方法

    公开(公告)号:US20060270245A1

    公开(公告)日:2006-11-30

    申请号:US10908833

    申请日:2005-05-27

    IPC分类号: H01L21/31

    摘要: The present invention relates to a bilayer cap structure for interconnect structures that comprise copper metallization or other conductive metallization. Such bilayer cap structure includes a first cap layer formed by an unbiased high density plasma (HDP) chemical vapor deposition process, and a second cap layer over the first cap layer, where the second cap layer is formed by a biased high density plasma (bHDP) chemical vapor deposition process. During the bHDP chemical vapor deposition process, a low AC bias power is applied to the substrate to increase the ion bombardment on the substrate surface and to induce resputtering of the capping material, thereby forming a seamless second cap layer with excellent reactive ion etching (RIE) selectivity.

    摘要翻译: 本发明涉及一种用于互连结构的双层盖结构,其包括铜金属化或其它导电金属化。 这种双层盖结构包括通过无偏高密度等离子体(HDP)化学气相沉积工艺形成的第一盖层和在第一盖层上的第二盖层,其中第二盖层由偏置的高密度等离子体(bHDP )化学气相沉积工艺。 在bHDP化学气相沉积工艺期间,将低AC偏置功率施加到衬底上以增加衬底表面上的离子轰击并引起封盖材料的再溅射,从而形成具有优异的反应离子蚀刻(RIE)的无缝第二帽层 )选择性。

    IMPROVED HDP-BASED ILD CAPPING LAYER
    10.
    发明申请
    IMPROVED HDP-BASED ILD CAPPING LAYER 有权
    改进的基于HDP的ILD捕获层

    公开(公告)号:US20060113672A1

    公开(公告)日:2006-06-01

    申请号:US10904827

    申请日:2004-12-01

    IPC分类号: H01L23/48 H01L23/58 H01L23/52

    摘要: A cap nitride stack which prevents etch penetration to the HDP nitride while maintaining the electromigration benefits of HDP nitride atop Cu. In one embodiment, the stack comprises a first layer of HDP nitride and a second layer of a Si—C—H compound disposed over the first layer. The Si—C—H compound is for example BLoK, or N-BLoK (Si—C—H—N), and is selected from a group of materials that has high selectivity during via RIE such that RIE chemistry from the next wiring level does not punch through. Carbon and nitrogen are the key elements. In another embodiment, the stack comprises a first layer of HDP nitride, followed by a second layer of UVN (a plasma nitride), and a third layer comprising HDP nitride disposed over the second layer.

    摘要翻译: 一种覆盖氮化物叠层,可以防止蚀刻渗透到HDP氮化物,同时保持在Cu顶部的HDP氮化物的电迁移效果。 在一个实施例中,堆叠包括第一层HDP氮化物和设置在第一层上的Si-C-H化合物的第二层。 Si-C-H化合物例如是BLoK或N-BLoK(Si-C-H-N),并且选自在通孔RIE期间具有高选择性的一组材料,使得来自下一个布线层的RIE化学不会穿透。 碳氮是关键要素。 在另一个实施例中,堆叠包括第一层HDP氮化物,随后是第二层UVN(等离子体氮化物),以及包含设置在第二层上的HDP氮化物的第三层。