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    Method for reducing short channel effects in memory cells and related structure
    1.
    发明授权
    Method for reducing short channel effects in memory cells and related structure 有权
    减少存储单元短路效应的方法及相关结构

    公开(公告)号：US06773990B1

    公开(公告)日：2004-08-10

    申请号：US10429150

    申请日：2003-05-03

    申请人： Richard Fastow ,  Yue-Song He ,  Kazuhiro Mizutani ,  Timothy Thurgate

    发明人： Richard Fastow ,  Yue-Song He ,  Kazuhiro Mizutani ,  Timothy Thurgate

    IPC分类号： H10L21336

    CPC分类号： H01L27/11521 ,  H01L27/115

    摘要： According to one exemplary embodiment, a method for fabricating a floating gate memory array comprises a step of removing a dielectric material from an isolation region situated in a substrate to expose a trench, where the trench is situated between a first source region and a second source region, where the trench defines sidewalls in the substrate. The method further comprises implanting an N type dopant in the first source region, the second source region, and the sidewalls of the trench, where the N type dopant forms an N+ type region. The method further comprises implanting a P type dopant in the first source region, the second source region, and the sidewalls of the trench, where the P type dopant forms a P type region, and where the P type region is situated underneath the N+ type region.

    摘要翻译： 根据一个示例性实施例，一种用于制造浮动栅极存储器阵列的方法包括从位于衬底中的隔离区域去除介电材料以暴露沟槽的步骤，其中沟槽位于第一源区域和第二源极之间 区域，其中沟槽限定衬底中的侧壁。 该方法还包括在第一源极区域，第二源极区域和沟槽的侧壁中注入N型掺杂剂，其中N型掺杂剂形成N +型区域。 该方法还包括在第一源极区域，第二源极区域和沟槽的侧壁中注入P型掺杂剂，其中P型掺杂剂形成P型区域，并且其中P型区域位于N +型下方 地区。

    Memory array with memory cells having reduced short channel effects
    2.
    发明授权
    Memory array with memory cells having reduced short channel effects 有权
    具有存储单元的存储器阵列具有减少的短通道效应

    公开(公告)号：US06963106B1

    公开(公告)日：2005-11-08

    申请号：US10839626

    申请日：2004-05-04

    申请人： Richard Fastow ,  Yue-Song He ,  Kazuhiro Mizutani ,  Timothy Thurgate

    发明人： Richard Fastow ,  Yue-Song He ,  Kazuhiro Mizutani ,  Timothy Thurgate

    IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L21/788

    CPC分类号： H01L27/11521 ,  H01L27/115

    摘要： According to one exemplary embodiment, a method for fabricating a floating gate memory array comprises a step of removing a dielectric material from an isolation region situated in a substrate to expose a trench, where the trench is situated between a first source region and a second source region, where the trench defines sidewalls in the substrate. The method further comprises implanting an N type dopant in the first source region, the second source region, and the sidewalls of the trench, where the N type dopant forms an N+ type region. The method further comprises implanting a P type dopant in the first source region, the second source region, and the sidewalls of the trench, where the P type dopant forms a P type region, and where the P type region is situated underneath the N+ type region.

    摘要翻译： 根据一个示例性实施例，一种用于制造浮动栅极存储器阵列的方法包括从位于衬底中的隔离区域去除介电材料以暴露沟槽的步骤，其中沟槽位于第一源区域和第二源极之间 区域，其中沟槽限定衬底中的侧壁。 该方法还包括在第一源极区域，第二源极区域和沟槽的侧壁中注入N型掺杂剂，其中N型掺杂剂形成N +型区域。 该方法还包括在第一源极区域，第二源极区域和沟槽的侧壁中注入P型掺杂剂，其中P型掺杂剂形成P型区域，并且其中P型区域位于N +型下方 地区。

    Apparatus and method for source side implantation after spacer formation to reduce short channel effects in metal oxide semiconductor field effect transistors
    3.
    发明授权
    Apparatus and method for source side implantation after spacer formation to reduce short channel effects in metal oxide semiconductor field effect transistors 有权
    间隔物形成后源侧注入的装置和方法，以减少金属氧化物半导体场效应晶体管的短沟道效应

    公开(公告)号：US08896048B1

    公开(公告)日：2014-11-25

    申请号：US10861581

    申请日：2004-06-04

    申请人： Richard Fastow ,  Zhigang Wang ,  Yue-Song He ,  Kazuhiro Mizutani ,  Pavel Fastenko

    发明人： Richard Fastow ,  Zhigang Wang ,  Yue-Song He ,  Kazuhiro Mizutani ,  Pavel Fastenko

    IPC分类号： H01L29/76

    CPC分类号： H01L29/66659 ,  H01L29/66825 ,  H01L29/7881

    摘要： The present invention provides an apparatus and method for a metal oxide semiconductor field effect transistor (MOSFET) fabricated to reduce short channel effects. The MOSFET includes a semiconductor substrate, a gate stack formed above the semiconductor substrate, a drain side sidewall spacer formed on a drain side of the gate stack, a source side sidewall spacer formed on a source side of the gate stack, and source and drain regions. The source region is formed in the semiconductor substrate on the source side, and is aligned by the source side sidewall spacer to extend an effective channel length between the source region and drain region. The drain region is formed on the drain side in the semiconductor substrate, and is aligned by drain side sidewall spacer to further extend the effective channel length.

    摘要翻译： 本发明提供一种制造用于减少短沟道效应的金属氧化物半导体场效应晶体管（MOSFET）的装置和方法。 MOSFET包括半导体衬底，形成在半导体衬底上方的栅极堆叠，形成在栅极堆叠的漏极侧的漏极侧壁间隔物，形成在栅极堆叠的源极侧的源极侧壁隔离物，以及源极和漏极 地区。 源极区域形成在源极侧的半导体衬底中，并且通过源极侧壁间隔物对齐以在源极区域和漏极区域之间延伸有效沟道长度。 漏极区域形成在半导体衬底的漏极侧，并且通过漏极侧壁间隔物排列以进一步延长有效沟道长度。

    Array type CAM cell for simplifying processes
    6.
    发明授权
    Array type CAM cell for simplifying processes 有权
    阵列型CAM单元，用于简化过程

    公开(公告)号：US08237210B1

    公开(公告)日：2012-08-07

    申请号：US11349562

    申请日：2006-02-08

    申请人： Zhigang Wang ,  Kazuhiro Mizutani ,  Richard Fastow

    发明人： Zhigang Wang ,  Kazuhiro Mizutani ,  Richard Fastow

    IPC分类号： H01L29/76

    CPC分类号： G11C15/00

    摘要： A semiconductor apparatus is presented that includes an array of memory cells. The memory cells are arranged in rows and columns. Non-intersecting shallow trench isolation regions isolate the columns of memory cells. Also included is at least one source region that is isolated between an adjoining pair of the non-intersecting shallow trench isolation regions and isolated from a drain region. The source region is coupled to source lines in the array of memory cells. A contact couples a select plurality of the columns of memory cells, the select plurality functioning as a single content addressable memory cell.

    摘要翻译： 提出了一种包括存储单元阵列的半导体装置。 存储单元以行和列排列。 不相交的浅沟槽隔离区域隔离存储单元的列。 还包括至少一个源极区域，其隔离在相邻的一对不相交的浅沟槽隔离区域之间并与漏极区域隔离。 源极区域耦合到存储器单元阵列中的源极线。 一个触点耦合选择的多个存储单元列，所述选择多个功能用作单个内容可寻址存储单元。

    Semiconductor device with STI and method for manufacturing the semiconductor device
    8.
    发明授权
    Semiconductor device with STI and method for manufacturing the semiconductor device 有权
    具有STI的半导体器件和用于制造半导体器件的方法

    公开(公告)号：US08497176B2

    公开(公告)日：2013-07-30

    申请号：US13164297

    申请日：2011-06-20

    申请人： Taiji Ema ,  Kazuhiro Mizutani

    发明人： Taiji Ema ,  Kazuhiro Mizutani

    IPC分类号： H01L21/336

    CPC分类号： H01L29/788 ,  H01L21/762 ,  H01L21/76232 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11536 ,  H01L27/11546 ,  H01L27/11548 ,  H01L27/11575 ,  H01L29/42336 ,  H01L29/7881

    摘要： A semiconductor device includes: a semiconductor substrate having first and second areas; an STI isolation region being made of an isolation trench formed in the semiconductor substrate and an insulating film burying the isolation trench and defining a plurality of active regions in the first and second areas; a first structure formed on an area from the active region in the first area to a nearby STI isolation region and having a first height; and a second structure formed on an area from the active region in the second area to a nearby STI isolation region and having a second height, wherein the surface of the said STI isolation region in the first area is lower than the surface of said STI isolation region in the second area.

    摘要翻译： 半导体器件包括：具有第一和第二区域的半导体衬底; STI隔离区域由形成在半导体衬底中的隔离沟道和绝缘膜构成，绝缘膜掩埋隔离沟槽并且在第一和第二区域中限定多个有源区域; 形成在从所述第一区域中的有源区域到附近的STI隔离区域并具有第一高度的区域上的第一结构; 以及形成在从所述第二区域中的有源区域到附近的STI隔离区域并具有第二高度的区域上的第二结构，其中所述第一区域中的所述STI隔离区域的表面低于所述STI隔离区域的表面 区域在第二区域。

    Method for forming a flash memory device with straight word lines
    9.
    发明授权
    Method for forming a flash memory device with straight word lines 有权
    用于形成具有直线字线的闪速存储器件的方法

    公开(公告)号：US07851306B2

    公开(公告)日：2010-12-14

    申请号：US12327641

    申请日：2008-12-03

    申请人： Shenqing Fang ,  Hiroyuki Ogawa ,  Kuo-Tung Chang ,  Pavel Fastenko ,  Kazuhiro Mizutani ,  Zhigang Wang

    发明人： Shenqing Fang ,  Hiroyuki Ogawa ,  Kuo-Tung Chang ,  Pavel Fastenko ,  Kazuhiro Mizutani ,  Zhigang Wang

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7883 ,  H01L21/2652 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825

    摘要： Embodiments of the present invention disclose a memory device having an array of flash memory cells with source contacts that facilitate straight word lines, and a method for producing the same. The array is comprised of a plurality of non-intersecting shallow trench isolation (STI) regions that isolate a plurality of memory cell columns. A source column is implanted with n-type dopants after the formation of a tunnel oxide layer and a first polysilicon layer. The implanted source column is coupled to a plurality of common source lines that are coupled to a plurality of source regions associated with memory cells in the array. A source contact is coupled to the implanted source column for providing electrical coupling with the plurality of source regions. The source contact is collinear with a row of drain contacts that are coupled to drain regions associated with a row of memory cells. The arrangement of source contacts collinear with the row of drain contacts allows for straight word line formation.

    摘要翻译： 本发明的实施例公开了一种存储器件，其具有具有促进直线字线的源极触点的闪存单元阵列及其制造方法。 阵列由隔离多个存储单元列的多个不相交的浅沟槽隔离（STI）区域组成。 在形成隧道氧化物层和第一多晶硅层之后，源极列注入n型掺杂剂。 植入的源极柱耦合到耦合到与阵列中的存储器单元相关联的多个源极区域的多个公共源极线。 源极触点耦合到植入源极柱，用于提供与多个源极区域的电耦合。 源触点与一排漏极触点共线，该排触点耦合到与一行存储器单元相关联的漏极区。 与漏极触点排共线的源触点的布置允许直线字线形成。

    Semiconductor device and method of manufacturing the same
    10.
    发明授权
    Semiconductor device and method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US06794244B2

    公开(公告)日：2004-09-21

    申请号：US10173595

    申请日：2002-06-19

    申请人： Kazuhiro Mizutani ,  Michiari Kawano

    发明人： Kazuhiro Mizutani ,  Michiari Kawano

    IPC分类号： H01L218242

    CPC分类号： H01L21/76831 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76883 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894

    摘要： There is provided a semiconductor device having a COB type DRAM, which comprises a first insulating film formed on a semiconductor substrate, first wiring trenches formed in a first insulating film in the first region, second wiring trenches formed in the first insulating film in the second region to have a substantially same depth as the first wiring trenches, first wirings buried in lower portions of the first wiring trenches, a second insulating film buried in upper portions of the first wiring trenches and formed of material different from the first insulating film, and second wirings formed of same conductive material as the first wirings in the second wiring trenches and formed thicker than the first wirings. Accordingly, the pattern precision of the bit lines and the wirings that have a different film thickness can be increased, and through holes that are formed between the bit lines in the self-alignment manner are formed shallow, and also resistances of the bit lines and the wirings are reduced.

    摘要翻译： 提供了具有COB型DRAM的半导体器件，其包括形成在半导体衬底上的第一绝缘膜，形成在第一区域中的第一绝缘膜中的第一布线沟槽，在第二绝缘膜中形成的第二布线沟槽 区域具有与第一布线沟槽基本相同的深度，埋在第一布线沟槽的下部的第一布线，埋在第一布线沟槽的上部并由不同于第一绝缘膜的材料形成的第二绝缘膜，以及 第二布线由与第二布线沟槽中的第一布线相同的导电材料形成并且形成为比第一布线更厚。 因此，可以提高具有不同膜厚度的位线和布线的图案精度，并且以自对准方式形成在位线之间的通孔形成浅，并且还具有位线和 布线减少。