公开(公告)号：US09285860B2

公开(公告)日：2016-03-15

申请号：US12772484

申请日：2010-05-03

申请人： Richard Gerard Hofmann

发明人： Richard Gerard Hofmann

IPC分类号： G06F1/32 ,  G06F1/04

CPC分类号： G06F1/3215 ,  G06F1/04 ,  G06F1/3237

摘要： An apparatus includes a communications port configured to communicate over a bus responsive to a clock signal and a clock signal generation circuit configured to generate the clock signal and to vary a gating hysteresis of the clock signal responsive to a control input, such as a communications transaction of the port. The clock signal generation circuit may be configured to vary the gating hysteresis of the clock signal based on an attribute of the transaction, such as an address of the transaction and/or a payload communicated in the transaction.

摘要翻译： 一种装置包括通信端口，其被配置为响应于时钟信号而通过总线进行通信，以及时钟信号生成电路，其被配置为产生时钟信号，并且响应于诸如通信事务的控制输入而改变时钟信号的门控迟滞 的港口。 时钟信号产生电路可以被配置为基于事务的属性（诸如交易的地址和/或交易中传送的有效载荷）来改变时钟信号的选通滞后。

公开(公告)号：US20130117593A1

公开(公告)日：2013-05-09

申请号：US13290250

申请日：2011-11-07

申请人： Prudhvi N. Nooney ,  Jaya Prakash Subramaniam Ganasan ,  Joseph L. Van Swearingen ,  Richard Gerard Hofmann

发明人： Prudhvi N. Nooney ,  Jaya Prakash Subramaniam Ganasan ,  Joseph L. Van Swearingen ,  Richard Gerard Hofmann

IPC分类号： G06F1/32

CPC分类号： G06F1/3237 ,  G06F1/3253 ,  Y02D10/128 ,  Y02D10/151 ,  Y02D50/20

摘要： A System-on-a-Chip (SoC) comprising a controller, an activity counter, a reference pattern detection logic, a master pattern detection logic, an arbiter, a comparator, a tracker circuit, a delay cell circuit, and a request mask circuit coupled to a bus. The bus is configured to support master control. The controller is configured to cause components to enter a low power state. The activity counter is configured to monitor activity. The detection logics are configured to operate on an activity based clock or always on clock. The arbiter is configured to select an initiator. The comparator is configured to compare the output of the detection logics. The tracker circuit is configured to track selection of components. The delay cell circuit is configured to store output of components. The request mask circuit is configured to prevent request to arbiter or any arbiter selected request made from a previous clock cycle.

摘要翻译： 一种片上系统（SoC），包括控制器，活动计数器，参考模式检测逻辑，主模式检测逻辑，仲裁器，比较器，跟踪器电路，延迟单元电路和请求掩码 电路耦合到总线。 总线配置为支持主控制。 控制器被配置为使组件进入低功率状态。 活动计数器配置为监视活动。 检测逻辑被配置为在基于活动的时钟上操作或者始终处于时钟上。 仲裁器被配置为选择启动器。 比较器配置为比较检测逻辑的输出。 跟踪器电路被配置为跟踪组件的选择。 延迟单元电路被配置为存储组件的输出。 请求屏蔽电路被配置为防止对仲裁器的请求或从先前时钟周期进行的任何仲裁器选择的请求。

公开(公告)号：US08028143B2

公开(公告)日：2011-09-27

申请号：US10929127

申请日：2004-08-27

申请人： Richard Gerard Hofmann ,  Mark Michael Schaffer

发明人： Richard Gerard Hofmann ,  Mark Michael Schaffer

IPC分类号： G06F12/00

CPC分类号： G06F9/383 ,  G06F12/0215 ,  G06F13/161

摘要： A processing system and method is disclosed wherein a processor may be configured to predict an address of memory from which data will be needed, transmit to a memory controller a pre-fetch command for the data at the predicted address of the memory, and transmit to the memory controller a read request for the data at the predicted address of the memory if the data is needed.

摘要翻译： 公开了一种处理系统和方法，其中处理器可以被配置为预测将需要数据的存储器的地址，向存储器控制器发送在存储器的预测地址处的数据的预取命令，并且发送到 如果需要数据，存储器控制器对存储器的预测地址处的数据的读请求。

公开(公告)号：US07617343B2

公开(公告)日：2009-11-10

申请号：US11070016

申请日：2005-03-02

申请人： Richard Gerard Hofmann ,  Mark Michael Schaffer

发明人： Richard Gerard Hofmann ,  Mark Michael Schaffer

IPC分类号： G06F13/42 ,  G06F13/00 ,  G06F13/36 ,  H04Q1/30 ,  H04L1/18

CPC分类号： G06F13/4265

摘要： A processing system is disclosed with a sending component and a receiving component connected by a bus. The bus may be configured with transmit and receive channels. The transmit channel may have a plurality of sub-channels. The sending component may be configured to broadcast on each of the sub-channels information comprising read and write address locations, read and write control signals, and write data on each of the sub-channels. The receiving component may be configured to store the write data and retrieve read data in response to the information broadcast on any of the sub-channels, and broadcast the retrieved read data on the receive channel to the sending component. The sending component may further be configured to provide to the receiving component independent signaling for each of the sub-channels, the independent signaling being sufficient to allow the receiving component to determine the type of information broadcast on each of the sub-channels.

摘要翻译： 公开了一种具有通过总线连接的发送部件和接收部件的处理系统。 总线可以配置有发送和接收通道。 发射信道可以具有多个子信道。 发送组件可以被配置为在每个子信道上广播包括读取和写入地址位置，读取和写入控制信号以及每个子信道上的写入数据的信息。 接收组件可以被配置为存储写入数据并且响应于在任何子信道上广播的信息来检索读取数据，并且将接收信道上检索到的读取数据广播到发送组件。 发送组件还可以被配置为向每个子信道的接收组件提供独立的信令，独立信令足以允许接收组件确定在每个子信道上广播的信息的类型。

公开(公告)号：US20070204091A1

公开(公告)日：2007-08-30

申请号：US11557119

申请日：2006-11-07

申请人： Richard Gerard Hofmann ,  Terence J. Lohman

发明人： Richard Gerard Hofmann ,  Terence J. Lohman

IPC分类号： G06F13/36

CPC分类号： G06F13/28 ,  G06F13/4022

摘要： A processing system and method for transferring data in a processing system. The processing system includes a bus mastering device, a plurality of slave devices, and a bus interconnect configured to switch the bus mastering device between the slave devices. Each of the slave devices has a plurality of addresses. The bus interconnect includes a DMA controller configured to transfer data from a first one of the addresses to a second one of the addresses in response to a single bus command from the bus mastering device.

摘要翻译： 一种用于在处理系统中传送数据的处理系统和方法。 处理系统包括总线主控装置，多个从设备和配置成在从设备之间切换总线主控装置的总线互连。 每个从设备具有多个地址。 总线互连包括DMA控制器，其被配置为响应于来自总线主控装置的单个总线命令，将数据从地址的第一个地址传送到第二个地址。

公开(公告)号：US20070176742A1

公开(公告)日：2007-08-02

申请号：US11553600

申请日：2006-10-27

申请人： Richard Gerard Hofmann ,  Gerald Paul Michalak ,  Barry Joe Wolford

发明人： Richard Gerard Hofmann ,  Gerald Paul Michalak ,  Barry Joe Wolford

IPC分类号： G08B5/22 ,  H04Q7/14

CPC分类号： H04M19/04 ,  H04M1/57 ,  H04M1/72547 ,  H04M19/044 ,  H04M19/047

摘要： In a meeting or group event, people having a portable device, such as a cell phone or pager, may wish to be discretely notified when an important message is received, an urgent call comes in from a selected person or a selected group of people, or to be alerted to an upcoming important event without any audible alert to disturb the meeting or group event. To convey such a notification, a tactile alert is provided by vibrating the portable device according to a unique vibration pattern associated with the received communication. When a communication is received, a group identification (ID) is assigned based on the communication being a member of a classified group of source addresses. The portable device associates the group ID with a unique vibration pattern. To provide the alert, the portable device is vibrated according to the unique vibration pattern.

摘要翻译： 在会议或小组活动中，具有诸如蜂窝电话或寻呼机的便携式设备的人可能希望在收到重要消息时离散地通知来自所选择的人或所选人群的紧急呼叫， 或者提醒未来的重要事件而没有任何可听见的警报来打扰会议或团体活动。 为了传达这种通知，通过根据与接收的通信相关联的唯一振动模式振动便携式设备来提供触觉警报。 当接收到通信时，基于作为分类的源地址组的成员的通信来分配组标识（ID）。 便携式设备将组ID与唯一的振动模式相关联。 为了提供警报，便携式设备根据独特的振动模式而振动。

公开(公告)号：US07035958B2

公开(公告)日：2006-04-25

申请号：US10264170

申请日：2002-10-03

申请人： Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Bernard Charles Drerup ,  Richard Gerard Hofmann ,  Thomas Andrew Sartorius ,  Barry Joe Wolford

发明人： Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Bernard Charles Drerup ,  Richard Gerard Hofmann ,  Thomas Andrew Sartorius ,  Barry Joe Wolford

IPC分类号： G06F13/36

CPC分类号： G06F13/362 ,  G06F13/4022 ,  G06F2213/0038

摘要： A method of operating a request FIFO of a system on a chip (SoC) in which a requests in a first position that has been granted and which subsequently receives a retry from the intended target is automatically re-ordered with respect to the other requests below it in the request FIFO. Each issued requests is tagged to either enable or disable a re-order feature. When a request that is tagged as re-order enabled is granted, the FIFO logic monitors the response provided for the request. If the response is a retry, the request is removed from the first position of the request FIFO and the next sequential request is moved into the first position. The removed requests may be re-ordered within the request FIFO or sent back to the initiator. In the former implementation, controller logic reorders the first request within the request FIFO. In the latter implementation, the controller logic of the bus controller messages the initiator when a request has been retried and subsequently removed from the first position of the request FIFO. The initiator then determines whether or not to re-issue the request.

摘要翻译： 一种操作芯片上系统（SoC）的请求FIFO的方法，其中已经被许可的第一个位置的请求和随后从预期目标接收到重试的请求自动地按照下面的其他请求重新排序 它在请求FIFO中。 每个发出的请求被标记为启用或禁用重新排序功能。 当被标记为启用重新排序的请求被授予时，FIFO逻辑监视为请求提供的响应。 如果响应是重试，则请求从请求FIFO的第一位置移除，并且下一个顺序请求被移动到第一位置。 删除的请求可以在请求FIFO内重新排序或发送回发起者。 在前面的实现中，控制器逻辑重新排序请求FIFO中的第一个请求。 在后一实现中，总线控制器的控制器逻辑在请求已被重试并随后从请求FIFO的第一位置移除时消息发起者。 然后，启动器确定是否重新发出请求。

公开(公告)号：US06857029B2

公开(公告)日：2005-02-15

申请号：US10137084

申请日：2002-04-30

申请人： Jaya Prakash Subramaniam Ganasan ,  Adger Erik Harvin, III ,  Richard Gerard Hofmann ,  Perry Willmann Remaklus, Jr.

发明人： Jaya Prakash Subramaniam Ganasan ,  Adger Erik Harvin, III ,  Richard Gerard Hofmann ,  Perry Willmann Remaklus, Jr.

IPC分类号： G06F1/12 ,  G06F13/00

CPC分类号： G06F1/12

摘要： A bus performance monitoring mechanism for systems on a chip (SOC) is disclosed. The system comprises a muxing logic adapted to be coupled to a plurality of master devices, a plurality of slave devices, a plurality of generic signals and a plurality of control signals. The monitoring mechanism includes a plurality of control registers coupled to the muxing logic to allow for the selection of master, slave, generic and pipeline stage events to be counted. Finally, the monitoring mechanism includes synchronizing logic coupled to the plurality of registers for providing and receiving synchronizing signals to and from the monitors coupled thereto to allow for scalability. The scalable on-chip bus performance monitoring system in accordance with the present invention performs on-chip bus monitoring within a SOC implementation, while eliminating the pitfalls as described above. Through a minimalistic design approach, scalability is easily accomplished through the concept of using multiple monitor instances of these monitoring mechanisms within an SOC design while maintaining synchronization among them. Should an SOC design increase in size, scalability is achieved by simply adding additional monitor instance(s). The multiple monitor instances could then be connected in a “lego-like” fashion, allowing each to operate independently, or concurrently with one another via a scalable synchronization technique. For these designs where multiple monitor instances may be required, this enhances wireability by allowing the SOC designer to scatter the monitor instance locations virtually anywhere within the smaller areas of unused chip space, and simply wire the synchronization signals among the monitor instances to allow for synchronous operation.

摘要翻译： 公开了一种用于芯片系统（SOC）的总线性能监视机制。 该系统包括适于耦合到多个主设备，多个从设备，多个通用信号和多个控制信号的多路复用逻辑。 监视机制包括耦合到多路复用逻辑的多个控制寄存器，以允许对主，从，通用和流水线级事件的选择进行计数。 最后，监视机制包括与多个寄存器耦合的同步逻辑，用于提供和接收与耦合到其的监视器同步信号以允许可扩展性。 根据本发明的可扩展的片上总线性能监视系统在SOC实现中执行片上总线监视，同时消除如上所述的陷阱。 通过简约的设计方法，可以通过在SOC设计中使用这些监视机制的多个监视器实例，同时保持它们之间的同步来实现可扩展性。 如果SOC设计的大小增加，则通过简单地添加附加的监视器实例来实现可扩展性。 然后，多个监视器实例可以以“lego-like”的方式连接，允许每个监视器实例通过可伸缩的同步技术独立地或彼此并行操作。 对于可能需要多个监视器实例的这些设计，通过允许SOC设计人员将监视器实例位置实际上分散在未使用的芯片空间的较小区域内的任何位置，从而提高了可线性，并且简单地将监视器实例之间的同步信号连接起来以允许同步 操作。

公开(公告)号：US06504854B1

公开(公告)日：2003-01-07

申请号：US09058724

申请日：1998-04-10

申请人： Richard Gerard Hofmann ,  Mark Michael Schaffer ,  Thomas Andrew Sartorius

发明人： Richard Gerard Hofmann ,  Mark Michael Schaffer ,  Thomas Andrew Sartorius

IPC分类号： H04J306

CPC分类号： G06F13/4059

摘要： A communication system is provided for use in processing systems and the like for carrying out data transfer operations between a first data bus and a peripheral device associated with a second data bus, wherein the first data bus operates at a first clock speed and wherein the second data bus operates. at a second clock speed which is different from the first clock speed and a 1/N integer multiple of the first clock speed. A sample signal associated with the second clock speed is received and the speed of operation of a state machine of a peripheral controller is dynamically adjusted in response to the sample signal such that the state machine of the peripheral controller operates at the second clock speed and causes operations on the second data bus to occur synchronously at the second clock speed.

摘要翻译： 提供了一种用于处理系统等的通信系统，用于在与第二数据总线相关联的第一数据总线和外围设备之间执行数据传输操作，其中第一数据总线以第一时钟速度操作，并且其中第二数据总线 数据总线运行。 以与第一时钟速度不同的第二时钟速度和第一时钟速度的1 / N整数倍。 接收与第二时钟速度相关联的采样信号，并且响应于采样信号动态地调整外围控制器的状态机的操作速度，使得外围控制器的状态机以第二时钟速度工作并导致 在第二数据总线上的操作以第二时钟速度同步地发生。

公开(公告)号：US6032238A

公开(公告)日：2000-02-29

申请号：US20123

申请日：1998-02-06

申请人： Edward Hammond Green, III ,  Richard Gerard Hofmann ,  Mark Michael Schaffer ,  Dennis Charles Wilkerson

发明人： Edward Hammond Green, III ,  Richard Gerard Hofmann ,  Mark Michael Schaffer ,  Dennis Charles Wilkerson

IPC分类号： G06F13/28 ,  G06F12/00

CPC分类号： G06F13/28

摘要： A method and apparatus is provided which allows overlapping of DMA line read and line write cycles. In an exemplary embodiment, the PLB Line Read Word Address bus is used with a DMA controller sideband signal to detect the conditions required to allow the DMA controller to start the line write one cycle prior to the completion of the line read cycle. A reference bit is set when the first word of a multi-word line transfer has been read. A sideband timing signal is generated one cycle prior to the completion of the read cycle indicating that there is only one read data phase remaining of the line read. If the first word to be written out to memory has been read or is available when the timing signal is generated, the write operation is begun prior to the final phase of the memory read transfer, and the read and write operations are overlapped thereby accomplishing an overlapped read/write transfer in fewer cycles than the sum of read and write transfer cycles if done sequentially.

摘要翻译： 提供了允许DMA线读取和行写入周期重叠的方法和装置。 在示例性实施例中，PLB线读取字地址总线与DMA控制器边带信号一起使用，以检测在线读取周期完成之前允许DMA控制器开始行写入一个周期所需的条件。 当读取多字行传输的第一个字时，设置一个参考位。 边缘定时信号在读周期完成之前一个周期产生，表示只读一行读取数据相位。 如果要在存储器中写入的第一个字已经被读取或在生成定时信号时可用，则在存储器读取传送的最后阶段之前开始写入操作，并且读取和写入操作重叠，从而完成 如果顺序完成，则读取/写入传输的循环次数比读取和写入传输周期的总和少。