公开(公告)号：US5023773A

公开(公告)日：1991-06-11

申请号：US154740

申请日：1988-02-10

申请人： Richard I. Baum ,  Terry L. Borden ,  Justin R. Butwell ,  Carl E. Clark ,  Alan G. Ganek ,  James Lum ,  Michael G. Mall ,  David R. Page ,  Kenneth E. Plambeck ,  Casper A. Scalzi ,  Richard J. Schmalz

发明人： Richard I. Baum ,  Terry L. Borden ,  Justin R. Butwell ,  Carl E. Clark ,  Alan G. Ganek ,  James Lum ,  Michael G. Mall ,  David R. Page ,  Kenneth E. Plambeck ,  Casper A. Scalzi ,  Richard J. Schmalz

IPC分类号： G06F12/08 ,  G06F9/46 ,  G06F12/10 ,  G06F12/14 ,  G06F21/24

CPC分类号： G06F9/468 ,  G06F12/1483

摘要： A program authorization mechanism for authorizing access to an address space in the main memory of a computer system by a program being run under a multiple address space facility. An access-list entry is associated with each address space, each access-list entry being designated by an access-list-entry token contained in an access register. Each access-list entry includes a private indicator which indicates if the associated address space can be accessed by all programs from this access-list entry or if the associated address space can only be accessed by an authorized program. For program to be authorized, an extended authorization index in a control register must match an access-list extended authorization index in the access-list entry, or the extended authorization index value must be authorized in an authority table associated with the address space. An instruction for testing a given extended authorization index for a given access-list-entry is also disclosed.

公开(公告)号：US4979098A

公开(公告)日：1990-12-18

申请号：US535248

申请日：1990-06-08

申请人： Richard I. Baum ,  Terry L. Borden ,  Justin R. Butwell ,  Carl E. Clark ,  Alan G. Ganek ,  James Lum ,  Michael G. Mall ,  Kenneth E. Plambeck ,  Casper A. Scalzi ,  Richard J. Schmalz ,  Ronald M. Smith ,  Julian Thomas

发明人： Richard I. Baum ,  Terry L. Borden ,  Justin R. Butwell ,  Carl E. Clark ,  Alan G. Ganek ,  James Lum ,  Michael G. Mall ,  Kenneth E. Plambeck ,  Casper A. Scalzi ,  Richard J. Schmalz ,  Ronald M. Smith ,  Julian Thomas

IPC分类号： G06F9/46 ,  G06F12/02 ,  G06F12/10 ,  G06F12/14

CPC分类号： G06F9/468 ,  G06F12/0292 ,  G06F12/1036 ,  G06F12/1483

摘要： A method and apparatus is provided to translate the contents of access registers into information for use in performing addressing functions for multiple virtual address spaces. The access registers represent the full addressing capability of the system but do not directly contain the addressing information. The system has a plurality of general purpose registers, a plurality of access registers associated with the general registers, an access list having access list entries which is addressed by the contents of the access register, memory storage for holding address space number second table entries (ASTE), where the contents of the access list entry locate the ASTE and where the ASTE contains the addressing information needed to translate a virtual address when combined with the contents of a general purpose register. Access register translation (ART) consists of the process of determining addressing information by using the access list entry and the ASTE. The results of the ART process are stored in an ART lookaside buffer (ALB) which stores the results of ART while valid for later use.

摘要翻译： 提供了一种方法和装置，用于将访问寄存器的内容转换为用于执行多个虚拟地址空间的寻址功能的信息。 访问寄存器表示系统的完整寻址能力，但不直接包含寻址信息。 该系统具有多个通用寄存器，与通用寄存器相关联的多个访问寄存器，具有由访问寄存器的内容寻址的访问列表条目的访问列表，用于保存地址空间数第二表条目的存储器存储 ASTE），其中访问列表条目的内容定位ASTE，并且ASTE包含当与通用寄存器的内容组合时将虚拟地址翻译所需的寻址信息。 访问注册翻译（ART）包括通过使用访问列表条目和ASTE来确定寻址信息的过程。 ART处理的结果存储在ART后视缓冲器（ALB）中，其存储ART的结果，有效期以后使用。

公开(公告)号：US5220669A

公开(公告)日：1993-06-15

申请号：US732936

申请日：1991-07-19

申请人： Richard I. Baum ,  Terry L. Borden ,  Carol E. Clark ,  Alan G. Ganek ,  James Lum ,  Michael G. Mall ,  Casper A. Scalzi ,  Richard J. Schmalz

发明人： Richard I. Baum ,  Terry L. Borden ,  Carol E. Clark ,  Alan G. Ganek ,  James Lum ,  Michael G. Mall ,  Casper A. Scalzi ,  Richard J. Schmalz

IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F9/46

CPC分类号： G06F9/30054 ,  G06F9/30076 ,  G06F9/3851 ,  G06F9/468

摘要： A computer system has general purpose registers, control registers and access registers for containing information to allow address space capability. A linkage stack uses protected address space to store state information during program call and program return operations. The linkage stack contains information relating to state entries for the saved information and header and trailer entries to point to other linkage stack sections. A control register contains the pointer to the current linkage stack entry and is changed as the program call or return moves through the stack.

摘要翻译： 计算机系统具有通用寄存器，控制寄存器和访问寄存器，用于包含允许地址空间能力的信息。 链接堆栈在程序调用和程序返回操作期间使用受保护的地址空间来存储状态信息。 链接堆栈包含与保存的信息的状态条目相关的信息，以及指向其他链接堆栈部分的报头和尾部条目。 控制寄存器包含指向当前链接堆栈条目的指针，并在程序调用或返回移动通过堆栈时更改。

公开(公告)号：US5381537A

公开(公告)日：1995-01-10

申请号：US803320

申请日：1991-12-06

申请人： Richard I. Baum ,  Kenneth E. Plambeck ,  Casper A. Scalzi ,  Richard J. Schmalz ,  Bhaskar Sinha

发明人： Richard I. Baum ,  Kenneth E. Plambeck ,  Casper A. Scalzi ,  Richard J. Schmalz ,  Bhaskar Sinha

IPC分类号： G06F12/10 ,  G06F12/02 ,  G06F12/00

CPC分类号： G06F12/0292

摘要： A method and apparatus for translating a large logical address as a large virtual address (LVA) when a dynamic address translation (DAT) mode is on. Each LVA is separated into three concatenated parts: 1. a highest-order part (ADEN) for indexing into an access directory (AD) to locate an entry (ADE) for locating one access list (AL); 2. an intermediate part (ALEN) for indexing into a selected AL to access an entry (ALE) that enables location of an associated conventional address translation table which represents a conventional size virtual address space; and 3. a low-order DAT virtual address (VA) part having the same size as a conventional type of virtual address. The low-order DAT VA part is translated by the associated conventional address translation table. If a carry signal is generated during the creation of the low-order DAT VA part, then a change in the selection of an ALE results. An offset value of ALEs can be utilized to generate an effective ADEN and ALEN, which are utilized for the address translation of the LVA.

摘要翻译： 当动态地址转换（DAT）模式打开时用于将大的逻辑地址翻译为大的虚拟地址（LVA）的方法和装置。 每个LVA被分成三个级联部分：1.用于索引到访问目录（AD）的最高阶部分（ADEN），以定位用于定位一个访问列表（AL）的条目（ADE）; 2.一种用于索引到所选择的AL以访问条目（ALE）的中间部分（ALEN），所述入口（ALE）使得能够定位表示常规大小的虚拟地址空间的相关联的常规地址转换表; 和3.具有与常规类型的虚拟地址相同大小的低阶DAT虚拟地址（VA）部分。 低阶DAT VA部分由相关联的常规地址转换表转换。 如果在创建低阶DAT VA部分期间产生进位信号，则会产生ALE选择的变化。 ALE的偏移值可用于生成有效的ADEN和ALEN，用于LVA的地址转换。

公开(公告)号：US4355355A

公开(公告)日：1982-10-19

申请号：US131570

申请日：1980-03-19

申请人： Justin R. Butwell ,  Casper A. Scalzi ,  Richard J. Schmalz

发明人： Justin R. Butwell ,  Casper A. Scalzi ,  Richard J. Schmalz

IPC分类号： G06F9/34 ,  G06F12/06 ,  G06F12/10 ,  G06F12/14 ,  G06F9/36

CPC分类号： G06F12/1475 ,  G06F12/0623 ,  G06F12/1036

摘要： The detailed embodiment associates access registers (AR's) with the general purpose registers (GPR's) in a data processor. The AR's are each loaded with a unique STD (segment table descriptor). The STD comprises a segment table address in main storage and a segment table length field. There are 15 AR's associated respectively with 15 GPR's in a processor to define a subset of up to 15 data address spaces. The STD in an AR is selected for address translation when the associated GPR is selected as a storage operand base register, such as being the GPR selected by the B-field in an IBM System/370 instruction. The invention allows each AR to specify that it does not use the STD in its associated AR to define its data address space, but instead uses the STD in the program address space AR. However, the STD content of an AR is not selected for an address translation if the associated GPR is selected for a purpose other than as a storage operand base register, such as if a GPR is selected as an index (X) register or as a data source or sink register (R) for an instruction. A sixteenth AR may be provided to define and control the executing program address space, which may also contain data.The embodiment obtains authority and other control for access to and use of the content in each address space by also associating an AR Control Vector (ARCV) register with each AR.

摘要翻译： 详细实施例将访问寄存器（AR）与通用寄存器（GPR）在数据处理器中相关联。 每个AR都加载了一个唯一的STD（段表描述符）。 STD包括主存储器中的段表地址和段表长度字段。 在处理器中有15个AR分别与15个GPR相关联，以定义多达15个数据地址空间的子集。 当选择相关联的GPR作为存储操作数基址寄存器时，AR中的STD被选择用于地址转换，例如由IBM System / 370指令中的B字段选择的GPR。 本发明允许每个AR指定它不使用其关联的AR中的STD来定义其数据地址空间，而是在程序地址空间AR中使用STD。 然而，如果相关联的GPR被选择用于除了作为存储操作数的基本寄存器之外的目的，例如如果选择GPR作为索引（X）寄存器或者作为索引（X）寄存器，则不选择AR的STD内容用于地址转换 用于指令的数据源或接收寄存器（R）。 可以提供第十六AR以定义和控制也可以包含数据的执行程序地址空间。 该实施例还通过将AR控制向量（ARCV）寄存器与每个AR相关联来获得对每个地址空间中的内容的访问和使用的权限和其他控制。

公开(公告)号：US5237668A

公开(公告)日：1993-08-17

申请号：US424797

申请日：1989-10-20

申请人： Geoffrey O. Blandy ,  David B. Emmes ,  Ronald F. Hill ,  David B. Lindquist ,  Kenneth E. Plambeck ,  Casper A. Scalzi ,  Richard J. Schmalz

发明人： Geoffrey O. Blandy ,  David B. Emmes ,  Ronald F. Hill ,  David B. Lindquist ,  Kenneth E. Plambeck ,  Casper A. Scalzi ,  Richard J. Schmalz

IPC分类号： G06F12/10 ,  G06F12/14

CPC分类号： G06F12/10 ,  G06F12/145

摘要： A single non-privileged instruction copies a page of data from a source virtual address in an electronic medium to a destination virtual address in the same or in a different electronic storage medium, and without the intervention of any supervisory program when each medium and the virtual addresses are previously determined. The instruction is not required to specify which medium it will use, does not require its user to know what backing medium it will access, does not require main storage (MS) to be its backing medium, and allows different types of physical addressing to be used by different media. The instruction can lock any page for use in a multi-processor (MP). No physical direction of data movement is provided within the non-privileged machine instruction, which only designates virtual direction of movement. The separation of virtual direction from physical direction is done by avoiding instruction control over selection of electronic media. The non-privileged instruction can nevertheless express a preference for obtaining a copy of the destination page in an electronic medium in which the content of the page can be processed by further instructions. Also, the instruction can cause invocation of a privileged control program to avoid the need for a following condition code test instruction. A privileged instruction is also provided to wait for the completion of the unprivileged instruction and to invalidate a non-MS medium page whether it is unlocked or locked, either correctly or incorrectly.

公开(公告)号：US5423013A

公开(公告)日：1995-06-06

申请号：US754810

申请日：1991-09-04

申请人： Richard I. Baum ,  Brent A. Carlson ,  Moon J. Kim ,  Michael G. Mall ,  Casper A. Scalzi ,  Bhaskar Sinha

发明人： Richard I. Baum ,  Brent A. Carlson ,  Moon J. Kim ,  Michael G. Mall ,  Casper A. Scalzi ,  Bhaskar Sinha

IPC分类号： G06F9/32 ,  G06F9/355 ,  G06F12/02 ,  G06F12/06 ,  G06F12/10 ,  G06F12/08

CPC分类号： G06F9/342 ,  G06F12/0292 ,  G06F12/0623 ,  G06F9/32 ,  G06F2212/206

摘要： Allows instructions and data to be located in any one or more of plural sections of a large-size real memory of a data processing system. Any memory section is located by concatenating a conventional small real/absolute address with an address extender used with conventional small-size memory. A Central Processor Extended Address Mode (CPEAM) register content indicates the location of extenders in an AR(s), ASTE(s), STE(s) or PTE(s) for use by a central processor or I/O operations. An Input-Output Extended Address Mode (IOEAM) register content indicates the location of the extenders in ORB(s), CCW(s) or IDAW(s) for use by I/O operations. A compatible mode sets the content to zero for either or both of the CPEAM and IOEAM if either or both is not to be used.

摘要翻译： 允许指令和数据位于数据处理系统的大尺寸实际存储器的多个部分中的任何一个或多个中。 任何存储器部分通过将传统的小实际/绝对地址与传统的小尺寸存储器使用的地址扩展器连接来定位。 中央处理器扩展地址模式（CPEAM）寄存器内容指示AR（s），ASTE，STE（s）或PTE的扩展器的位置，供中央处理器或I / O操作使用。 输入输出扩展地址模式（IOEAM）寄存器内容指示扩展器在ORB（s），CCW（s）或IDAW中的位置，供I / O操作使用。 如果不使用任何一个或两个，则兼容模式将CPEAM和IOEAM中的一个或两个设置为零。

公开(公告)号：US5361356A

公开(公告)日：1994-11-01

申请号：US847521

申请日：1992-03-06

申请人： Carl E. Clark ,  Jeffrey A. Frey ,  Kenneth E. Plambeck ,  Casper A. Scalzi ,  Bhaskar Sinha

发明人： Carl E. Clark ,  Jeffrey A. Frey ,  Kenneth E. Plambeck ,  Casper A. Scalzi ,  Bhaskar Sinha

IPC分类号： G06F12/10 ,  G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F9/46 ,  G06F9/40

CPC分类号： G06F9/30054 ,  G06F9/30003 ,  G06F9/3851 ,  G06F9/468

摘要： A Branch in Subspace Group (BSG) instruction is executed in problem state (for example by an application program) for providing a fast instruction branch between address spaces within a restricted group of address spaces called a subspace group. The subspace group contains two types of address spaces: a base space and any number of subspaces. The subspace group is set up in a control table associated with each dispatchable unit (DU). This DU control table contains: an identifier of a base space, an identifier of an access list that contains identifiers of all subspaces in the subspace group, an indicator of whether CPU control was last given to a subspace or to the base space, and an identifier of a last entered subspace in the group. The BSG instruction has an operand defining a general register containing the target virtual address and an associated access register containing an access-list-entry token (ALET) defining the target address space. The ALET indexes to a target subspace identifier in the access list, and then the associated virtual address locates the target instruction in the identified target address space. BSG instruction execution controls restrict the BSG branching only to an instruction in the subspace group.

摘要翻译： 子空间组（BSG）中的分支在问题状态（例如由应用程序）执行，用于在被称为子空间组的受限制的一组地址空间内的地址空间之间提供快速指令分支。 子空间组包含两种类型的地址空间：基本空间和任何数量的子空间。 子空间组设置在与每个可调度单元（DU）相关联的控制表中。 该DU控制表包含：基本空间的标识符，包含子空间组中所有子空间的标识符的访问列表的标识符，CPU控制是否被最后给予子空间或基本空间的指示符，以及 组中最后输入的子空间的标识符。 BSG指令具有定义包含目标虚拟地址的通用寄存器的操作数和包含定义目标地址空间的访问列表入口令牌（ALET）的关联访问寄存器。 ALET索引到访问列表中的目标子空间标识符，然后相关联的虚拟地址将目标指令定位在所识别的目标地址空间中。 BSG指令执行控制将BSG分支限制到子空间组中的指令。

公开(公告)号：US5163096A

公开(公告)日：1992-11-10

申请号：US710875

申请日：1991-06-06

申请人： Carl E. Clark ,  Michael G. Mall ,  Casper A. Scalzi ,  Bhaskar Sinha

发明人： Carl E. Clark ,  Michael G. Mall ,  Casper A. Scalzi ,  Bhaskar Sinha

IPC分类号： G06F12/14 ,  G06F21/24

CPC分类号： G06F12/1491

摘要： Provides three access levels of storage key protection, comprising a supervisory level (key 0), an intermediate level of non-public and non-supervisory keys (keys 1-8, 10-15), and an unique public level (key 9). The program routines operating with a supervisory-level access key can access both the public level and the intermediate level of storage blocks. Although a program routine operating with an access key in the intermediary access level cannot access any supervisory level storage block, it can access any block assigned a public level storage key, as well as any storage block assigned the respective intermediate level key. One or more third-level public storage keys (PSKs) may be provided. A program access key using one of the PSK values can only access blocks having the same PSK value, and it cannot access blocks having any other key value.

摘要翻译： 提供存储密钥保护的三个访问级别，包括监控级别（密钥0），非公共和非监督密钥（密钥1-8,10-15）的中间级别和唯一的公共级别（密钥9） 。 使用监控级访问密钥操作的程序例程可以访问存储块的公共级和中级级别。 虽然以中间访问级别中的访问密钥操作的程序例程不能访问任何监督级存储块，但是它可以访问分配了公共级存储密钥的任何块以及分配给各个中间级密钥的任何存储块。 可以提供一个或多个第三级公共存储密钥（PSK）。 使用PSK值之一的程序访问密钥只能访问具有相同PSK值的块，并且它不能访问具有任何其他密钥值的块。

公开(公告)号：US5454086A

公开(公告)日：1995-09-26

申请号：US928937

申请日：1992-08-11

申请人： Alan I. Alpert ,  Carl E. Clark ,  Michel H. T. Hack ,  Casper A. Scalzi ,  Richard J. Schmalz, deceased ,  Bhaskar Sinha

发明人： Alan I. Alpert ,  Carl E. Clark ,  Michel H. T. Hack ,  Casper A. Scalzi ,  Richard J. Schmalz, deceased ,  Bhaskar Sinha

IPC分类号： G06F11/28 ,  G06F9/40 ,  G06F11/36 ,  G06F9/00 ,  G06F11/00

CPC分类号： G06F11/3636 ,  G06F9/4425

摘要： Provides a dynamic execution link between an analyzer program and each hook instruction in a program. Special types of hook instructions are provided for use in a hooked program. The link causes the analyzer program to execute as part of a continuous uninterrupted execution for each hook instruction. The link uses hardware and/or internal code to access a hook control area which provides linkage information needed to invoke the execution of the analyzer program upon completion of the hook instruction and to continue the execution of the hooked program following the completion of the analyzer program. The linkage information includes the entry location into the analyzer program, and also locates the first hook work area (HWA) of a sequence of HWAs, from which an HWA is assigned to each current hook instruction. The assigned HWA stores a return point location in the hooked program at an instruction following the current hook instruction. One or more hooked programs may concurrently use the same analyzer program. As soon as execution by the analyzer program ends for a hook instruction, its assigned HWA is released for use by another hook instruction.

摘要翻译： 在分析程序与程序中的每个挂钩指令之间提供动态执行链接。 提供特殊类型的挂钩指令用于挂钩程序。 该链接使分析程序作为每个挂钩指令的连续不间断执行的一部分执行。 该链接使用硬件和/或内部代码访问挂钩控制区域，其提供在完成钩指令时调用分析器程序的执行所需的链接信息，并且在分析器程序完成之后继续执行挂钩程序 。 链接信息包括进入分析器程序的入口位置，并且还定位HWAs序列的第一挂钩工作区域（HWA），HWA被分配给每个当前挂钩指令。 所分配的HWA在当前挂钩指令之后的指令处在挂钩程序中存储返回点位置。 一个或多个挂钩程序可以同时使用相同的分析程序。 一旦分析程序的执行结束为​​一个挂接指令，其分配的HWA被释放供另一个钩子指令使用。