公开(公告)号：US20080311745A1

公开(公告)日：2008-12-18

申请号：US12197845

申请日：2008-08-25

申请人： Ricky Amos ,  Douglas A. Buchanan ,  Cyril Cabral, JR. ,  Alessandro C. Callegari ,  Supratik Guha ,  Hyungjun Kim ,  Fenton R. McFeely ,  Vijay Narayanan ,  Kenneth P. Rodbell ,  John J. Yurkas

发明人： Ricky Amos ,  Douglas A. Buchanan ,  Cyril Cabral, JR. ,  Alessandro C. Callegari ,  Supratik Guha ,  Hyungjun Kim ,  Fenton R. McFeely ,  Vijay Narayanan ,  Kenneth P. Rodbell ,  John J. Yurkas

IPC分类号： H01L21/44

CPC分类号： H01L29/495 ,  H01L21/28079 ,  H01L21/3003

摘要： A method for fabricating a CMOS gate electrode by using Re, Rh, Pt, Ir or Ru metal and a CMOS structure that contains such gate electrodes are described. The work functions of these metals make them compatible with current pFET requirements. For instance, the metal can withstand the high hydrogen pressures necessary to produce properly passivated interfaces without undergoing chemical changes. The thermal stability of the metal on dielectric layers such as SiO2, Al2O3 and other suitable dielectric materials makes it compatible with post-processing temperatures up to 1000° C. A low temperature/low pressure CVD technique with Re2(CO)10 as the source material is used when Re is to be deposited.

摘要翻译： 描述了通过使用Re，Rh，Pt，Ir或Ru金属制造CMOS栅电极的方法和包含这种栅电极的CMOS结构。 这些金属的工作功能使其与当前的pFET要求兼容。 例如，金属可以承受生产适当钝化界面而不经历化学变化所需的高氢气压力。 金属在介电层上的热稳定性如SiO 2，Al 2 O 3和其它合适的介电材料使其与后处理温度高达1000℃相兼容。具有Re2（CO）10作为源的低温/低压CVD技术 当Re沉积时使用材料。

公开(公告)号：US20090152642A1

公开(公告)日：2009-06-18

申请号：US12355368

申请日：2009-01-16

申请人： Nestor A. Bojarczuk, JR. ,  Cyril Cabral, JR. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

发明人： Nestor A. Bojarczuk, JR. ,  Cyril Cabral, JR. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

IPC分类号： H01L27/092 ,  H01L21/336 ,  H01L21/02

CPC分类号： H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride. A second gate stack of an nFET devices is located on top remaining device channels, the second gate stack including a high-k gate dielectric and a fully silicided gate electrode located directly atop the high-k gate dielectric.

摘要翻译： 本发明提供一种半导体结构，其包括具有位于其中的多个源极和漏极扩散区域的半导体衬底，每对源极和漏极扩散区域由器件沟道分离。 该结构还包括位于一些器件通道顶部的pFET器件的第一栅极堆叠，第一栅极堆叠包括高k栅极电介质，邻接栅极电介质的绝缘夹层和邻接绝缘体的完全硅化金属栅电极 中间层，绝缘中间层包括将p-FET器件的阈值电压和扁平带电压稳定到目标值的绝缘金属氮化物，并且是氮氧化铝，氮化硼，氮氧化硼，氮化镓，氮氧化镓，氮化铟和铟中的一种 氮氧化物。 nFET器件的第二栅极堆叠位于顶部剩余器件沟道上，第二栅极堆叠包括高k栅极电介质和直接位于高k栅极电介质顶部的完全硅化栅电极。

公开(公告)号：US20110165767A1

公开(公告)日：2011-07-07

申请号：US13047172

申请日：2011-03-14

申请人： Nestor A. Bojarczuk, JR. ,  Cyril Cabral, JR. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

发明人： Nestor A. Bojarczuk, JR. ,  Cyril Cabral, JR. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

IPC分类号： H01L21/28

CPC分类号： H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride. A second gate stack of an nFET devices is located on top remaining device channels, the second gate stack including a high-k gate dielectric and a fully silicided gate electrode located directly atop the high-k gate dielectric.

摘要翻译： 本发明提供一种半导体结构，其包括具有位于其中的多个源极和漏极扩散区域的半导体衬底，每对源极和漏极扩散区域由器件沟道分离。 该结构还包括位于一些器件通道顶部的pFET器件的第一栅极堆叠，第一栅极堆叠包括高k栅极电介质，邻接栅极电介质的绝缘夹层和邻接绝缘体的完全硅化金属栅电极 中间层，绝缘中间层包括将p-FET器件的阈值电压和扁平带电压稳定到目标值的绝缘金属氮化物，并且是氮氧化铝，氮化硼，氮氧化硼，氮化镓，氮氧化镓，氮化铟和铟中的一种 氮氧化物。 nFET器件的第二栅极堆叠位于顶部剩余器件沟道上，第二栅极堆叠包括高k栅极电介质和直接位于高k栅极电介质顶部的完全硅化栅电极。

公开(公告)号：US20090011610A1

公开(公告)日：2009-01-08

申请号：US12211530

申请日：2008-09-16

申请人： Nestor A. Bojarczuk, JR. ,  Cyril Cabral, JR. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

发明人： Nestor A. Bojarczuk, JR. ,  Cyril Cabral, JR. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

IPC分类号： H01L21/31

CPC分类号： H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be AlN or AlOxNy. The high k dielectric can be HfO2, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HCl/H2O2 peroxide solution.

摘要翻译： 一种形成CMOS结构的方法及其制造的器件，具有改进的阈值电压和平带电压稳定性。 本发明的方法包括提供具有nFET区和pFET区的半导体衬底的步骤; 在所述半导体衬底上形成包括在高k电介质顶上的绝缘夹层的电介质叠层; 从nFET区域去除绝缘中间层而不从pFET区域去除绝缘中间层; 以及在pFET区域中提供至少一个栅极堆叠以及在nFET区域中提供至少一个栅极堆叠。 绝缘中间层可以是AlN或AlOxNy。 高k电介质可以是HfO 2，硅酸铪或铪硅氮氧化物。 可以通过包括HCl / H2O2过氧化物溶液的湿蚀刻从nFET区域去除绝缘中间层。

公开(公告)号：US20130062769A1

公开(公告)日：2013-03-14

申请号：US13232085

申请日：2011-09-14

申请人： Cyril Cabral, JR. ,  Takeshi Nogami ,  Jeffrey P. Gambino ,  Qiang Huang ,  Kenneth P. Rodbell

发明人： Cyril Cabral, JR. ,  Takeshi Nogami ,  Jeffrey P. Gambino ,  Qiang Huang ,  Kenneth P. Rodbell

IPC分类号： H01L23/535 ,  H01L21/768

CPC分类号： H01L21/7684 ,  H01L21/2885 ,  H01L21/76841 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal interconnect structure and a method of manufacturing the metal interconnect structure. Manganese (Mn) is incorporated into a copper (Cu) interconnect structure in order to modify the microstructure to achieve bamboo-style grain boundaries in sub-90 nm technologies. Preferably, bamboo grains are separated at distances less than the “Blech” length so that copper (Cu) diffusion through grain boundaries is avoided. The added Mn also triggers the growth of Cu grains down to the bottom surface of the metal line so that a true bamboo microstructure reaching to the bottom surface is formed and the Cu diffusion mechanism along grain boundaries oriented along the length of the metal line is eliminated.

摘要翻译： 金属互连结构和金属互连结构的制造方法。 锰（Mn）被掺入到铜（Cu）互连结构中，以便在90nm以下的技术中改变微观结构以实现竹型晶界。 优选地，竹颗粒在小于Blech长度的距离处分离，使得避免通过晶界的铜（Cu）扩散。 添加的Mn还触发Cu颗粒向金属线底部的生长，从而形成达到底面的真正的竹结构，消除沿着金属线长度取向的晶界的Cu扩散机理 。

公开(公告)号：US20130001784A1

公开(公告)日：2013-01-03

申请号：US13611363

申请日：2012-09-12

申请人： Cyril Cabral, JR. ,  John M. Cotte ,  Kathryn C. Fisher ,  Laura L. Kosbar ,  Christian Lavoie ,  Zhu Liu ,  Kenneth P. Rodbell ,  Xiaoyan Shao

发明人： Cyril Cabral, JR. ,  John M. Cotte ,  Kathryn C. Fisher ,  Laura L. Kosbar ,  Christian Lavoie ,  Zhu Liu ,  Kenneth P. Rodbell ,  Xiaoyan Shao

IPC分类号： H01L23/48

CPC分类号： H01L21/28518 ,  H01L21/76841 ,  H01L23/53238 ,  H01L31/022408 ,  H01L31/022425 ,  H01L2924/0002 ,  Y02E10/50 ,  H01L2924/00

摘要： A semiconductor device or a photovoltaic cell having a contact structure, which includes a silicon (Si) substrate; a metal alloy layer deposited on the silicon substrate; a metal silicide layer and a diffusion layer formed simultaneously from thermal annealing the metal alloy layer; and a metal layer deposited on the metal silicide and barrier layers.

摘要翻译： 具有接触结构的半导体器件或光电池，其包括硅（Si）衬底; 沉积在硅衬底上的金属合金层; 金属硅化物层和由金属合金层热退火同时形成的扩散层; 以及沉积在金属硅化物和阻挡层上的金属层。

公开(公告)号：US20110309508A1

公开(公告)日：2011-12-22

申请号：US12819634

申请日：2010-06-21

申请人： Cyril Cabral, JR. ,  John M. Cotte ,  Kathryn C. Fisher ,  Laura L. Kosbar ,  Christian Lavoie ,  Zhu Liu ,  Kenneth P. Rodbell ,  Xiaoyan Shao

发明人： Cyril Cabral, JR. ,  John M. Cotte ,  Kathryn C. Fisher ,  Laura L. Kosbar ,  Christian Lavoie ,  Zhu Liu ,  Kenneth P. Rodbell ,  Xiaoyan Shao

IPC分类号： H01L23/485 ,  H01L21/768

CPC分类号： H01L21/28518 ,  H01L21/76841 ,  H01L23/53238 ,  H01L31/022408 ,  H01L31/022425 ,  H01L2924/0002 ,  Y02E10/50 ,  H01L2924/00

摘要： A semiconductor device or a photovoltaic cell having a contact structure, which includes a silicon (Si) substrate; a metal alloy layer deposited on the silicon substrate; a metal silicide layer and a diffusion layer formed simultaneously from thermal annealing the metal alloy layer; and a metal layer deposited on the metal silicide and barrier layers.

摘要翻译： 具有接触结构的半导体器件或光电池，其包括硅（Si）衬底; 沉积在硅衬底上的金属合金层; 金属硅化物层和由金属合金层热退火同时形成的扩散层; 以及沉积在金属硅化物和阻挡层上的金属层。

公开(公告)号：US20090315182A1

公开(公告)日：2009-12-24

申请号：US12145163

申请日：2008-06-24

申请人： Paul R. Besser ,  Christian Lavoie ,  Cyril Cabral, JR. ,  Stephen M. Rossnagel ,  Kenneth P. Rodbell

发明人： Paul R. Besser ,  Christian Lavoie ,  Cyril Cabral, JR. ,  Stephen M. Rossnagel ,  Kenneth P. Rodbell

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L21/76889 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76879 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53271 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming an interconnect structure includes forming a dielectric layer above a first layer having a conductive region defined therein. An opening is defined in the dielectric layer to expose at least a portion of the conductive region. A metal silicide is formed in the opening to define the interconnect structure. A semiconductor device includes a first layer having a conductive region defined therein, a dielectric layer formed above the first layer, and a metal silicide interconnect structure extending through the dielectric layer to communicate with the conductive region.

摘要翻译： 形成互连结构的方法包括在其中限定有导电区域的第一层之上形成介电层。 在电介质层中限定开口以暴露导电区域的至少一部分。 在开口中形成金属硅化物以限定互连结构。 半导体器件包括其中限定有导电区域的第一层，形成在第一层之上的电介质层和延伸穿过介电层以与导电区域连通的金属硅化物互连结构。

公开(公告)号：US20110127438A1

公开(公告)日：2011-06-02

申请号：US12627076

申请日：2009-11-30

申请人： Cyril Cabral, JR. ,  Michael S. Gordon ,  Steven J. Koester ,  Conal E. Murray ,  Kenneth P. Rodbell ,  Stephen M. Rossnagel ,  Robert L. Wisnieff ,  Jeng-bang Yau

发明人： Cyril Cabral, JR. ,  Michael S. Gordon ,  Steven J. Koester ,  Conal E. Murray ,  Kenneth P. Rodbell ,  Stephen M. Rossnagel ,  Robert L. Wisnieff ,  Jeng-bang Yau

IPC分类号： G01T1/02 ,  G01T3/00

CPC分类号： G01T1/026

摘要： A system for determining an amount of radiation includes a dosimeter configured to receive the amount of radiation, the dosimeter comprising a circuit having a resonant frequency, such that the resonant frequency of the circuit changes according to the amount of radiation received by the dosimeter, the dosimeter further configured to absorb RF energy at the resonant frequency of the circuit; a radio frequency (RF) transmitter configured to transmit the RF energy at the resonant frequency to the dosimeter; and a receiver configured to determine the resonant frequency of the dosimeter based on the absorbed RF energy, wherein the amount of radiation is determined based on the resonant frequency.

摘要翻译： 用于确定辐射量的系统包括配置成接收辐射量的剂量计，该剂量计包括具有谐振频率的电路，使得电路的谐振频率根据剂量计接收的辐射量而改变， 剂量计还被配置为吸收电路的谐振频率处的RF能量; 射频（RF）发射器，被配置为以共振频率将所述RF能量传输到所述剂量计; 以及接收器，被配置为基于所吸收的RF能量来确定所述剂量计的谐振频率，其中所述辐射量基于所述谐振频率来确定。

公开(公告)号：US20090243053A1

公开(公告)日：2009-10-01

申请号：US12483364

申请日：2009-06-12

申请人： Cyril Cabral, JR. ,  Michael S. Gordon ,  Kenneth P. Rodbell

发明人： Cyril Cabral, JR. ,  Michael S. Gordon ,  Kenneth P. Rodbell

IPC分类号： H01L23/556

CPC分类号： H01L23/556 ,  H01L21/76801 ,  H01L21/76834 ,  H01L21/76838 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L24/12 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05006 ,  H01L2224/05554 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01055 ,  H01L2924/01057 ,  H01L2924/01063 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/01092 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15312 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/05552

摘要： A structure for reduction of soft error rates in integrated circuits. The structure including: a semiconductor substrate; and a stack of one or more wiring levels stacked from a lowermost wiring level to an uppermost wiring level, the lowermost wiring level nearer the semiconductor substrate than the uppermost wiring level; and an alpha particle blocking layer on a top surface of the uppermost wiring level of the one or more wiring levels, the blocking layer comprising metal wires and a dielectric material, the blocking layer having a combination of a thickness of the blocking layer and a volume percent of metal wires in the blocking layer sufficient to stop a predetermined percentage of alpha particles of a selected energy or less striking the blocking layer from penetrating into the stack of one or more wiring levels or the substrate.

摘要翻译： 用于降低集成电路中软错误率的结构。 该结构包括：半导体衬底; 以及从最下布线电平堆叠到最上布线电平的一个或多个布线电平的堆叠，比最上布线电平更靠近半导体基板的最下布线电平; 以及在所述一个或多个布线层的最上布线层的顶表面上的α粒子阻挡层，所述阻挡层包括金属线和介电材料，所述阻挡层具有阻挡层的厚度和体积 阻挡层中的金属线的百分比足以阻止预定百分比的选定能量的α粒子或更少的击穿阻挡层的金属线穿透到一个或多个布线层或衬底的堆叠中。