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1.发明申请High Temperature Processing Compatible Metal Gate Electrode For pFETS and Methods For Fabrication 有权用于pFET的高温加工兼容金属栅电极和制造方法公开(公告)号：US20080311745A1
公开(公告)日：2008-12-18
申请号：US12197845
申请日：2008-08-25
申请人： Ricky Amos , Douglas A. Buchanan , Cyril Cabral, JR. , Alessandro C. Callegari , Supratik Guha , Hyungjun Kim , Fenton R. McFeely , Vijay Narayanan , Kenneth P. Rodbell , John J. Yurkas
发明人： Ricky Amos , Douglas A. Buchanan , Cyril Cabral, JR. , Alessandro C. Callegari , Supratik Guha , Hyungjun Kim , Fenton R. McFeely , Vijay Narayanan , Kenneth P. Rodbell , John J. Yurkas
IPC分类号： H01L21/44
CPC分类号： H01L29/495 , H01L21/28079 , H01L21/3003
摘要： A method for fabricating a CMOS gate electrode by using Re, Rh, Pt, Ir or Ru metal and a CMOS structure that contains such gate electrodes are described. The work functions of these metals make them compatible with current pFET requirements. For instance, the metal can withstand the high hydrogen pressures necessary to produce properly passivated interfaces without undergoing chemical changes. The thermal stability of the metal on dielectric layers such as SiO2, Al2O3 and other suitable dielectric materials makes it compatible with post-processing temperatures up to 1000° C. A low temperature/low pressure CVD technique with Re2(CO)10 as the source material is used when Re is to be deposited.
摘要翻译： 描述了通过使用Re，Rh，Pt，Ir或Ru金属制造CMOS栅电极的方法和包含这种栅电极的CMOS结构。 这些金属的工作功能使其与当前的pFET要求兼容。 例如，金属可以承受生产适当钝化界面而不经历化学变化所需的高氢气压力。 金属在介电层上的热稳定性如SiO 2，Al 2 O 3和其它合适的介电材料使其与后处理温度高达1000℃相兼容。具有Re2（CO）10作为源的低温/低压CVD技术 当Re沉积时使用材料。
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2.发明授权High temperature processing compatible metal gate electrode for pFETS and methods for fabrication 有权用于pFETS的高温处理兼容金属栅电极及其制造方法公开(公告)号：US07863083B2
公开(公告)日：2011-01-04
申请号：US12197845
申请日：2008-08-25
申请人： Ricky Amos , Douglas A. Buchanan , Cyril Cabral, Jr. , Alessandro C. Callegari , Supratik Guha , Hyungjun Kim , Fenton R. McFeely , Vijay Narayanan , Kenneth P. Rodbell , John J. Yurkas
发明人： Ricky Amos , Douglas A. Buchanan , Cyril Cabral, Jr. , Alessandro C. Callegari , Supratik Guha , Hyungjun Kim , Fenton R. McFeely , Vijay Narayanan , Kenneth P. Rodbell , John J. Yurkas
IPC分类号： H01L21/00 , H01L21/76 , H01L21/266 , H01L21/425
CPC分类号： H01L29/495 , H01L21/28079 , H01L21/3003
摘要： A method for fabricating a CMOS gate electrode by using Re, Rh, Pt, Ir or Ru metal and a CMOS structure that contains such gate electrodes are described. The work functions of these metals make them compatible with current pFET requirements. For instance, the metal can withstand the high hydrogen pressures necessary to produce properly passivated interfaces without undergoing chemical changes. The thermal stability of the metal on dielectric layers such as SiO2, Al2O3 and other suitable dielectric materials makes it compatible with post-processing temperatures up to 1000° C. A low temperature/low pressure CVD technique with Re2(CO)10 as the source material is used when Re is to be deposited.
摘要翻译： 描述了通过使用Re，Rh，Pt，Ir或Ru金属制造CMOS栅电极的方法和包含这种栅电极的CMOS结构。 这些金属的工作功能使其与当前的pFET要求兼容。 例如，金属可以承受生产适当钝化界面而不经历化学变化所需的高氢气压力。 金属在介电层上的热稳定性如SiO 2，Al 2 O 3和其它合适的介电材料使其与后处理温度高达1000℃相兼容。具有Re2（CO）10作为源的低温/低压CVD技术 当Re沉积时使用材料。
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公开(公告)号：US07023064B2
公开(公告)日：2006-04-04
申请号：US10710063
申请日：2004-06-16
IPC分类号： H01L29/76
CPC分类号： H01L21/823842 , H01L21/823857 , Y10S257/90 , Y10S438/942
摘要： An integrated circuit is provided including an FET gate structure formed on a substrate. This structure includes a gate dielectric on the substrate, and a metal nitride layer overlying the gate dielectric and in contact therewith. This metal nitride layer is characterized as MNx, where M is one of W, Re, Zr, and Hf, and x is in the range of about 0.7 to about 1.5. Preferably the layer is of WNx, and x is about 0.9. Varying the nitrogen concentration in the nitride layer permits integration of different FET characteristics on the same chip. In particular, varying x in the WNx layer permits adjustment of the threshold voltage in the different FETs. The polysilicon depletion effect is substantially reduced, and the gate structure can be made thermally stable up to about 1000° C.
摘要翻译： 提供了一种集成电路，其包括形成在衬底上的FET栅极结构。 该结构包括衬底上的栅极电介质和覆盖栅极电介质并与其接触的金属氮化物层。 该金属氮化物层的特征在于MN x，其中M是W，Re，Zr和Hf之一，x在约0.7至约1.5的范围内。 优选地，该层为W N x X，x为约0.9。 改变氮化物层中的氮浓度允许在同一芯片上集成不同的FET特性。 特别地，在WN 层中改变x允许调节不同FET中的阈值电压。 多晶硅耗尽效应显着降低，并且栅极结构可以在高达约1000℃下热稳定。
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4.发明授权公开(公告)号：US07998842B2
公开(公告)日：2011-08-16
申请号：US11214211
申请日：2005-08-29
IPC分类号： H01L21/285
CPC分类号： H01L21/28088 , H01L21/28562 , H01L21/32053 , H01L21/76841 , H01L29/4966 , H01L2221/1078
摘要： The present invention provides metallic films containing a Group IVB or VB metal, silicon and optionally nitrogen by utilizing atomic layer deposition (ALD). In particularly, the present invention provides a low temperature thermal ALD method of forming metallic silicides and a plasma-enhanced atomic layer deposition (PE-ALD) method of forming metallic silicon nitride film. The methods of the present invention are capable of forming metallic films having a thickness of a monolayer or less on the surface of a substrate. The metallic films provided in the present invention can be used for contact metallization, metal gates or as a diffusion barrier.
摘要翻译： 本发明通过利用原子层沉积（ALD）提供含有IVB族或VB族金属，硅和任选的氮的金属膜。 特别地，本发明提供形成金属硅化物的低温热ALD方法和形成金属氮化硅膜的等离子体增强原子层沉积（PE-ALD）方法。 本发明的方法能够在基材的表面上形成厚度为单层或更薄的金属膜。 本发明中提供的金属膜可用于接触金属化，金属栅极或扩散阻挡层。
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公开(公告)号：US07282403B2
公开(公告)日：2007-10-16
申请号：US11203952
申请日：2005-08-15
IPC分类号： H01L21/8238 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/823842 , H01L21/823857 , Y10S257/90 , Y10S438/942
摘要： An integrated circuit is provided including an FET gate structure formed on a substrate. This structure includes a gate dielectric on the substrate, and a metal nitride layer overlying the gate dielectric and in contact therewith. This metal nitride layer is characterized as MNx, where M is one of W, Re, Zr, and Hf, and x is in the range of about 0.7 to about 1.5. Preferably the layer is of WNx, and x is about 0.9. Varying the nitrogen concentration in the nitride layer permits integration of different FET characteristics on the same chip. In particular, varying x in the WNx layer permits adjustment of the threshold voltage in the different FETs. The polysilicon depletion effect is substantially reduced, and the gate structure can be made thermally stable up to about 1000° C.
摘要翻译： 提供了一种集成电路，其包括形成在衬底上的FET栅极结构。 该结构包括衬底上的栅极电介质和覆盖栅极电介质并与其接触的金属氮化物层。 该金属氮化物层的特征在于MN x，其中M是W，Re，Zr和Hf之一，x在约0.7至约1.5的范围内。 优选地，该层为W N x X，x为约0.9。 改变氮化物层中的氮浓度允许在同一芯片上集成不同的FET特性。 特别地，在WN 层中改变x允许调节不同FET中的阈值电压。 多晶硅耗尽效应显着降低，并且栅极结构可以在高达约1000℃下热稳定。
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公开(公告)号：US07098537B2
公开(公告)日：2006-08-29
申请号：US10707117
申请日：2003-11-21
CPC分类号： H01L21/76843 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： In an interconnect structure of an integrated circuit, a diffusion barrier film in a damascene structure is formed of a film having the composition TaNx, where x is greater than 1.2 and with a thickness of 0.5 to 5 nm.
摘要翻译： 在集成电路的互连结构中，镶嵌结构中的扩散阻挡膜由具有组成TaN x x的膜形成，其中x大于1.2，厚度为0.5至5nm 。
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7.发明授权Method of forming an interconnect structure diffusion barrier with high nitrogen content 有权形成具有高氮含量的互连结构扩散阻挡层的方法公开(公告)号：US07378338B2
公开(公告)日：2008-05-27
申请号：US11461220
申请日：2006-07-31
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： In an interconnect structure of an integrated circuit, a diffusion barrier film in a damascene structure is formed of a film having the composition TaNx, where x is greater than 1.2 and with a thickness of 0.5 to 5 nm.
摘要翻译： 在集成电路的互连结构中，镶嵌结构中的扩散阻挡膜由具有组成TaN x x的膜形成，其中x大于1.2，厚度为0.5至5nm 。
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8.发明授权公开(公告)号：US06943097B2
公开(公告)日：2005-09-13
申请号：US10643534
申请日：2003-08-19
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L29/49
CPC分类号： H01L21/28088 , H01L21/28562 , H01L21/32053 , H01L21/76841 , H01L29/4966 , H01L2221/1078
摘要： The present invention provides metallic films containing a Group IVB or VB metal, silicon and optionally nitrogen by utilizing atomic layer deposition (ALD). In particularly, the present invention provides a low temperature thermal ALD method of forming metallic silicides and a plasma-enhanced atomic layer deposition (PE-ALD) method of forming metallic silicon nitride film. The methods of the present invention are capable of forming metallic films having a thickness of a monolayer or less on the surface of a substrate. The metallic films provided in the present invention can be used for contact metallization, metal gates or as a diffusion barrier.
摘要翻译： 本发明通过利用原子层沉积（ALD）提供含有IVB族或VB族金属，硅和任选的氮的金属膜。 特别地，本发明提供形成金属硅化物的低温热ALD方法和形成金属氮化硅膜的等离子体增强原子层沉积（PE-ALD）方法。 本发明的方法能够在基材的表面上形成厚度为单层或更薄的金属膜。 本发明中提供的金属膜可用于接触金属化，金属栅极或扩散阻挡层。
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9.发明授权公开(公告)号：US06770500B2
公开(公告)日：2004-08-03
申请号：US10099004
申请日：2002-03-15
申请人： Alessandro Cesare Callegari , Christopher P. D'emic , Hyungjun Kim , Fenton Read McFeely , Vijay Narayanan , John Jacob Yurkas
发明人： Alessandro Cesare Callegari , Christopher P. D'emic , Hyungjun Kim , Fenton Read McFeely , Vijay Narayanan , John Jacob Yurkas
IPC分类号： H01L2100
CPC分类号： H01L21/823828 , H01L21/28079 , H01L21/3003
摘要： A process of passivating a metal-gated CMOS structure in which a metal-gated CMOS structure is passivated in an atmosphere of molecular hydrogen at a temperature of between about 250° C. and about 500° C. and a pressure of at least about 200 Torr. The present process provides a lower interface state density than obtainable by prior art passivation processes.
摘要翻译： 钝化金属门控CMOS结构的方法，其中金属门控CMOS结构在分子氢气氛中在约250℃至约500℃的温度和至少约200℃的压力下钝化 托尔 本方法提供比通过现有技术的钝化工艺可获得的更低的界面状态密度。
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10.发明申请METHOD OF PE-ALD OF SiNxCy AND INTEGRATION OF LINER MATERIALS ON POROUS LOW K SUBSTRATES 审中-公开SiNxCy的PE-AlD方法和多孔低K基体上衬层材料的整合公开(公告)号：US20120301706A1
公开(公告)日：2012-11-29
申请号：US13568808
申请日：2012-08-07
申请人： Andrew J. Kellock , Hyungjun Kim , Dae-Gyu Park , Satyanarayana V. Nitta , Sampath Purushothaman , Stephen Rossnagel , Oscar Van Der Straten
发明人： Andrew J. Kellock , Hyungjun Kim , Dae-Gyu Park , Satyanarayana V. Nitta , Sampath Purushothaman , Stephen Rossnagel , Oscar Van Der Straten
CPC分类号： C23C16/45536 , C23C16/36 , H01L21/02126 , H01L21/02167 , H01L21/0217 , H01L21/022 , H01L21/02203 , H01L21/02219 , H01L21/02274 , H01L21/0228 , H01L21/02315 , H01L21/3141 , H01L21/3148 , H01L21/31695 , H01L21/3185 , H01L21/76826 , H01L21/76831 , Y10T428/24999
摘要： A method of depositing a SiNxCy liner on a porous low thermal conductivity (low-k) substrate by plasma-enhanced atomic layer deposition (PE-ALD), which includes forming a SiNxCy liner on a surface of a low-k substrate having pores on a surface thereon, in which the low-k substrate is repeatedly exposed to a aminosilane-based precursor and a plasma selected from nitrogen, hydrogen, oxygen, helium, and combinations thereof until a thickness of the liner is obtained, and wherein the liner is prevented from penetrating inside the pores of a surface of the substrate. A porous low thermal conductivity substrate having a SiNxCy liner formed thereon by the method is also disclosed.
摘要翻译： 一种通过等离子体增强原子层沉积（PE-ALD）在多孔低热导率（低k）衬底上沉积SiNxCy衬垫的方法，其包括在具有孔的低k衬底的表面上形成SiN xCy衬垫 其中低k衬底反复暴露于基于氨基硅烷的前体和选自氮，氢，氧，氦及其组合的等离子体，直到获得衬垫的厚度，并且其中衬垫是 防止在基板的表面的孔内渗透。 还公开了通过该方法在其上形成SiN xCy衬垫的多孔低热导率衬底。
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