公开(公告)号：US07863083B2

公开(公告)日：2011-01-04

申请号：US12197845

申请日：2008-08-25

申请人： Ricky Amos ,  Douglas A. Buchanan ,  Cyril Cabral, Jr. ,  Alessandro C. Callegari ,  Supratik Guha ,  Hyungjun Kim ,  Fenton R. McFeely ,  Vijay Narayanan ,  Kenneth P. Rodbell ,  John J. Yurkas

发明人： Ricky Amos ,  Douglas A. Buchanan ,  Cyril Cabral, Jr. ,  Alessandro C. Callegari ,  Supratik Guha ,  Hyungjun Kim ,  Fenton R. McFeely ,  Vijay Narayanan ,  Kenneth P. Rodbell ,  John J. Yurkas

IPC分类号： H01L21/00 ,  H01L21/76 ,  H01L21/266 ,  H01L21/425

CPC分类号： H01L29/495 ,  H01L21/28079 ,  H01L21/3003

摘要： A method for fabricating a CMOS gate electrode by using Re, Rh, Pt, Ir or Ru metal and a CMOS structure that contains such gate electrodes are described. The work functions of these metals make them compatible with current pFET requirements. For instance, the metal can withstand the high hydrogen pressures necessary to produce properly passivated interfaces without undergoing chemical changes. The thermal stability of the metal on dielectric layers such as SiO2, Al2O3 and other suitable dielectric materials makes it compatible with post-processing temperatures up to 1000° C. A low temperature/low pressure CVD technique with Re2(CO)10 as the source material is used when Re is to be deposited.

摘要翻译： 描述了通过使用Re，Rh，Pt，Ir或Ru金属制造CMOS栅电极的方法和包含这种栅电极的CMOS结构。 这些金属的工作功能使其与当前的pFET要求兼容。 例如，金属可以承受生产适当钝化界面而不经历化学变化所需的高氢气压力。 金属在介电层上的热稳定性如SiO 2，Al 2 O 3和其它合适的介电材料使其与后处理温度高达1000℃相兼容。具有Re2（CO）10作为源的低温/低压CVD技术 当Re沉积时使用材料。

公开(公告)号：US20080311745A1

公开(公告)日：2008-12-18

申请号：US12197845

申请日：2008-08-25

申请人： Ricky Amos ,  Douglas A. Buchanan ,  Cyril Cabral, JR. ,  Alessandro C. Callegari ,  Supratik Guha ,  Hyungjun Kim ,  Fenton R. McFeely ,  Vijay Narayanan ,  Kenneth P. Rodbell ,  John J. Yurkas

发明人： Ricky Amos ,  Douglas A. Buchanan ,  Cyril Cabral, JR. ,  Alessandro C. Callegari ,  Supratik Guha ,  Hyungjun Kim ,  Fenton R. McFeely ,  Vijay Narayanan ,  Kenneth P. Rodbell ,  John J. Yurkas

IPC分类号： H01L21/44

CPC分类号： H01L29/495 ,  H01L21/28079 ,  H01L21/3003

摘要： A method for fabricating a CMOS gate electrode by using Re, Rh, Pt, Ir or Ru metal and a CMOS structure that contains such gate electrodes are described. The work functions of these metals make them compatible with current pFET requirements. For instance, the metal can withstand the high hydrogen pressures necessary to produce properly passivated interfaces without undergoing chemical changes. The thermal stability of the metal on dielectric layers such as SiO2, Al2O3 and other suitable dielectric materials makes it compatible with post-processing temperatures up to 1000° C. A low temperature/low pressure CVD technique with Re2(CO)10 as the source material is used when Re is to be deposited.

摘要翻译： 描述了通过使用Re，Rh，Pt，Ir或Ru金属制造CMOS栅电极的方法和包含这种栅电极的CMOS结构。 这些金属的工作功能使其与当前的pFET要求兼容。 例如，金属可以承受生产适当钝化界面而不经历化学变化所需的高氢气压力。 金属在介电层上的热稳定性如SiO 2，Al 2 O 3和其它合适的介电材料使其与后处理温度高达1000℃相兼容。具有Re2（CO）10作为源的低温/低压CVD技术 当Re沉积时使用材料。

公开(公告)号：US06452276B1

公开(公告)日：2002-09-17

申请号：US09070394

申请日：1998-04-30

申请人： Stephan A. Cohen ,  Fenton R. McFeely ,  Cevdet I. Noyan ,  Kenneth P. Rodbell ,  John J. Yurkas ,  Robert Rosenberg

发明人： Stephan A. Cohen ,  Fenton R. McFeely ,  Cevdet I. Noyan ,  Kenneth P. Rodbell ,  John J. Yurkas ,  Robert Rosenberg

IPC分类号： H01L2348

CPC分类号： H01L21/7687 ,  H01L21/76843 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention is directed to an alpha-W layer which is employed in interconnect structures such as trench capacitors or damascene wiring levels as a diffusion barrier layer. The alpha-W layer is a single phased material that is formed by a low temperature/pressure chemical vapor deposition process using tungsten hexacarbonyl, W(CO)6, as the source material.

公开(公告)号：US08293643B2

公开(公告)日：2012-10-23

申请号：US12819634

申请日：2010-06-21

申请人： Cyril Cabral, Jr. ,  John M. Cotte ,  Kathryn C. Fisher ,  Laura L. Kosbar ,  Christian Lavoie ,  Zhu Liu ,  Kenneth P. Rodbell ,  Xiaoyan Shao

发明人： Cyril Cabral, Jr. ,  John M. Cotte ,  Kathryn C. Fisher ,  Laura L. Kosbar ,  Christian Lavoie ,  Zhu Liu ,  Kenneth P. Rodbell ,  Xiaoyan Shao

IPC分类号： H01L21/477

CPC分类号： H01L21/28518 ,  H01L21/76841 ,  H01L23/53238 ,  H01L31/022408 ,  H01L31/022425 ,  H01L2924/0002 ,  Y02E10/50 ,  H01L2924/00

摘要： A semiconductor device or a photovoltaic cell having a contact structure, which includes a silicon (Si) substrate; a metal alloy layer deposited on the silicon substrate; a metal silicide layer and a diffusion layer formed simultaneously from thermal annealing the metal alloy layer; and a metal layer deposited on the metal silicide and barrier layers.

摘要翻译： 具有接触结构的半导体器件或光电池，其包括硅（Si）衬底; 沉积在硅衬底上的金属合金层; 金属硅化物层和由金属合金层热退火同时形成的扩散层; 以及沉积在金属硅化物和阻挡层上的金属层。

公开(公告)号：US07381635B2

公开(公告)日：2008-06-03

申请号：US11183647

申请日：2005-07-18

申请人： Cyril Cabral, Jr. ,  Michael S. Gordon ,  Kenneth P. Rodbell

发明人： Cyril Cabral, Jr. ,  Michael S. Gordon ,  Kenneth P. Rodbell

IPC分类号： H01L21/44

CPC分类号： H01L23/556 ,  H01L21/76801 ,  H01L21/76834 ,  H01L21/76838 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L24/12 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05006 ,  H01L2224/05554 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01055 ,  H01L2924/01057 ,  H01L2924/01063 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/01092 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15312 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/05552

摘要： A structure and a method for reduction of soft error rates in integrated circuits. The structure including: a semiconductor substrate; and a stack of one or more wiring levels stacked from a lowermost wiring level to an uppermost wiring level, the lowermost wiring level nearer the semiconductor substrate than the uppermost wiring level; and an alpha particle blocking layer on a top surface of the uppermost wiring level of the one or more wiring levels, the blocking layer comprising metal wires and a dielectric material, the blocking layer having a combination of a thickness of the blocking layer and a volume percent of metal wires in the blocking layer sufficient to stop a predetermined percentage of alpha particles of a selected energy or less striking the blocking layer from penetrating into the stack of one or more wiring levels or the substrate.

摘要翻译： 降低集成电路中软错误率的结构和方法。 该结构包括：半导体衬底; 以及从最下布线电平堆叠到最上布线电平的一个或多个布线电平的堆叠，比最上布线电平更靠近半导体基板的最下布线电平; 以及在所述一个或多个布线层的最上布线层的顶表面上的α粒子阻挡层，所述阻挡层包括金属线和介电材料，所述阻挡层具有阻挡层的厚度和体积 阻挡层中的金属线的百分比足以阻止预定百分比的选定能量的α粒子或更少的击穿阻挡层的金属线穿透到一个或多个布线层或衬底的堆叠中。

公开(公告)号：US06979393B2

公开(公告)日：2005-12-27

申请号：US10055134

申请日：2002-01-22

申请人： Kenneth P. Rodbell ,  Panayotis C. Andricacos ,  Cyril Cabral, Jr. ,  Lynne M. Gignac ,  Cyprian E. Uzoh ,  Peter S. Locke

发明人： Kenneth P. Rodbell ,  Panayotis C. Andricacos ,  Cyril Cabral, Jr. ,  Lynne M. Gignac ,  Cyprian E. Uzoh ,  Peter S. Locke

IPC分类号： C25D3/38 ,  C25D5/00 ,  C25D5/10 ,  C25D7/12 ,  H05K3/42 ,  C25D5/02

CPC分类号： C25D5/10 ,  C25D3/38 ,  C25D5/00 ,  C25D7/123 ,  C25D21/02 ,  H05K3/423

摘要： A method for plating copper conductors on an electronic substrate and devices formed are disclosed. In the method, an electroplating copper bath that is filled with an electroplating solution kept at a temperature between about 0° C. and about 18° C. is first provided. A copper layer on the electronic substrate immersed in the electroplating solution is then plated either in a single step or in a dual-step deposition process. The dual-step deposition process is more suitable for depositing copper conductors in features that have large aspect ratios, such as a via hole in a dual damascene structure having an aspect ratio of diameter/depth of more than ⅓ or as high as 1/10. Various electroplating parameters are utilized to provide a short resistance transient in either the single step deposition or the dual-step deposition process. These parameters include the bath temperature, the bath agitation, the additive concentration in the plating bath, the plating current density utilized, the deposition rate of the copper film and the total thickness of the copper film deposited.

摘要翻译： 公开了一种在电子基板上镀铜导体的方法和形成的器件。 在该方法中，首先提供填充有保持在约0℃至约18℃之间的温度的电镀溶液的电镀铜浴。 然后将浸在电镀溶液中的电子基板上的铜层以单步骤或双步沉积工艺进行镀覆。 双步沉积方法更适合于在具有大纵横比的特征中沉积铜导体，例如具有大于1/3或高达1的直径/深度的纵横比的双镶嵌结构中的通孔 / 10。 各种电镀参数用于在单步沉积或双步沉积过程中提供短电阻瞬变。 这些参数包括浴温度，浴液搅拌，镀浴中的添加剂浓度，所用的电镀电流密度，铜膜的沉积速率和沉积的铜膜的总厚度。

公开(公告)号：US08928145B2

公开(公告)日：2015-01-06

申请号：US13533182

申请日：2012-06-26

申请人： Paul Stephen Andry ,  Cyril Cabral, Jr. ,  Kenneth P. Rodbell ,  Robert L. Wisnieff

发明人： Paul Stephen Andry ,  Cyril Cabral, Jr. ,  Kenneth P. Rodbell ,  Robert L. Wisnieff

IPC分类号： H01L23/556 ,  H01L23/00

CPC分类号： H01L23/556 ,  H01L21/304 ,  H01L21/481 ,  H01L24/11 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/16 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29111 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/2064 ,  H01L2924/3025 ,  H01L2224/13111 ,  H01L2924/00014

摘要： A structure and system for forming the structure. The structure includes a semiconductor chip and an interposing shield having a top side and a bottom side. The semiconductor chip includes N chip electric pads, wherein N is a positive integer of at least 2. The N chip electric pads are electrically connected to a plurality of devices on the semiconductor chip. The electric shield includes 2N electric conductors and N shield electric pads. Each shield electrical pad is in electrical contact and direct physical contact with a corresponding pair of electric conductors of the 2N electric conductors. The interposing shield includes a shield material. The shield material includes a first semiconductor material. The semiconductor chip is bonded to the top side of the interposing shield. Each chip electric pads is in electrical contact and direct physical contact with a corresponding shield electrical pad of the N shield electric pads.

摘要翻译： 用于形成结构的结构和系统。 该结构包括半导体芯片和具有顶侧和底侧的插入屏蔽。 半导体芯片包括N个芯片电极焊盘，其中N是至少为2的正整数。N个芯片电极焊盘与半导体芯片上的多个器件电连接。 电气屏蔽包括2N个导电体和N个屏蔽电极垫。 每个屏蔽电焊垫与2N电导体的相应电导体电接触并直接物理接触。 中间屏蔽包括屏蔽材料。 屏蔽材料包括第一半导体材料。 半导体芯片被结合到插入式屏蔽的顶侧。 每个芯片电焊盘与N个屏蔽电焊盘的相应屏蔽电焊垫电接触并直接物理接触。

公开(公告)号：US20120028458A1

公开(公告)日：2012-02-02

申请号：US12052881

申请日：2008-03-21

申请人： Cyril Cabral, JR. ,  K. Paul Muller ,  Kenneth P. Rodbell

发明人： Cyril Cabral, JR. ,  K. Paul Muller ,  Kenneth P. Rodbell

IPC分类号： H01L21/768 ,  H01L23/556

CPC分类号： H01L23/5223 ,  H01L23/3192 ,  H01L23/53238 ,  H01L23/556 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/02166 ,  H01L2224/03831 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/10125 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/13007 ,  H01L2224/13028 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/13487 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81447 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2224/05552 ,  H01L2924/00

摘要： An alpha particle blocking structure and method of making the structure. The structure includes: a semiconductor substrate; a set of interlevel dielectric layers stacked from a lowermost interlevel dielectric layer closest to the substrate to a uppermost interlevel dielectric layer furthest from the substrate, each interlevel dielectric layer of the set of interlevel dielectric layers including electrically conductive wires, top surfaces of the wires substantially coplanar with top surfaces of corresponding interlevel dielectric layers; an electrically conductive terminal pad contacting a wire pad of the uppermost interlevel dielectric layer; an electrically conductive plating base layer contacting a top surface of the terminal pad; and a copper block on the plating base layer.

摘要翻译： 一种α粒子阻挡结构及其制造方法。 该结构包括：半导体衬底; 一组层间电介质层，从最靠近衬底的最下层的层间电介质层堆叠到距离衬底最远的最上层的层间电介质层，层间电介质层组中的每个层间电介质层包括导电线，电线的顶表面基本上 与对应的层间电介质层的顶表面共面; 接触最上层间介质层的焊盘的导电端子焊盘; 与所述端子焊盘的顶表面接触的导电电镀基层; 以及镀覆基底层上的铜块。

公开(公告)号：US07781871B2

公开(公告)日：2010-08-24

申请号：US12483364

申请日：2009-06-12

申请人： Cyril Cabral, Jr. ,  Michael S. Gordon ,  Kenneth P. Rodbell

发明人： Cyril Cabral, Jr. ,  Michael S. Gordon ,  Kenneth P. Rodbell

IPC分类号： H01L23/552

CPC分类号： H01L23/556 ,  H01L21/76801 ,  H01L21/76834 ,  H01L21/76838 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L24/12 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05006 ,  H01L2224/05554 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01055 ,  H01L2924/01057 ,  H01L2924/01063 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/01092 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15312 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/05552

摘要： A structure for reduction of soft error rates in integrated circuits. The structure including: a semiconductor substrate; and a stack of one or more wiring levels stacked from a lowermost wiring level to an uppermost wiring level, the lowermost wiring level nearer the semiconductor substrate than the uppermost wiring level; and an alpha particle blocking layer on a top surface of the uppermost wiring level of the one or more wiring levels, the blocking layer comprising metal wires and a dielectric material, the blocking layer having a combination of a thickness of the blocking layer and a volume percent of metal wires in the blocking layer sufficient to stop a predetermined percentage of alpha particles of a selected energy or less striking the blocking layer from penetrating into the stack of one or more wiring levels or the substrate.

摘要翻译： 用于降低集成电路中软错误率的结构。 该结构包括：半导体衬底; 以及从最下布线电平堆叠到最上布线电平的一个或多个布线电平的堆叠，比最上布线电平更靠近半导体基板的最下布线电平; 以及在所述一个或多个布线层的最上布线层的顶表面上的α粒子阻挡层，所述阻挡层包括金属线和介电材料，所述阻挡层具有阻挡层的厚度和体积 阻挡层中的金属线的百分比足以阻止预定百分比的选定能量的α粒子或更少的击穿阻挡层的金属线穿透到一个或多个布线层或衬底的堆叠中。

公开(公告)号：US08492897B2

公开(公告)日：2013-07-23

申请号：US13232085

申请日：2011-09-14

申请人： Cyril Cabral, Jr. ,  Jeffrey P. Gambino ,  Qiang Huang ,  Takeshi Nogami ,  Kenneth P. Rodbell

发明人： Cyril Cabral, Jr. ,  Jeffrey P. Gambino ,  Qiang Huang ,  Takeshi Nogami ,  Kenneth P. Rodbell

IPC分类号： H01L23/48

CPC分类号： H01L21/7684 ,  H01L21/2885 ,  H01L21/76841 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal interconnect structure and a method of manufacturing the metal interconnect structure. Manganese (Mn) is incorporated into a copper (Cu) interconnect structure in order to modify the microstructure to achieve bamboo-style grain boundaries in sub-90 nm technologies. Preferably, bamboo grains are separated at distances less than the “Blech” length so that copper (Cu) diffusion through grain boundaries is avoided. The added Mn also triggers the growth of Cu grains down to the bottom surface of the metal line so that a true bamboo microstructure reaching to the bottom surface is formed and the Cu diffusion mechanism along grain boundaries oriented along the length of the metal line is eliminated.

摘要翻译： 金属互连结构和金属互连结构的制造方法。 锰（Mn）被掺入到铜（Cu）互连结构中，以便在90nm以下的技术中改变微观结构以实现竹型晶界。 优选地，竹颗粒在小于“漂白”长度的距离处分离，以便避免通过晶界的铜（Cu）扩散。 添加的Mn还触发Cu颗粒向金属线底部的生长，从而形成达到底面的真正的竹结构，消除沿着金属线长度取向的晶界的Cu扩散机理 。