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1.发明申请公开(公告)号：US20110254129A1
公开(公告)日：2011-10-20
申请号：US13171320
申请日：2011-06-28
Applicant: Rishikesh Krishnan , Dan Gealy , Vidya Srividya , Noel Rocklein
Inventor： Rishikesh Krishnan , Dan Gealy , Vidya Srividya , Noel Rocklein
CPC classification number: H01G4/255 , H01L27/10852 , H01L28/65
Abstract: Electrical components for microelectronic devices and methods for forming electrical components. One particular embodiment of such a method comprises depositing an underlying layer onto a workpiece, and forming a conductive layer on the underlying layer. The method can continue by disposing a dielectric layer on the conductive layer. The underlying layer is a material that causes the dielectric layer to have a higher dielectric constant than without the underlying layer being present under the conductive layer. For example, the underlying layer can impart a structure or another property to the film stack that causes an otherwise amorphous dielectric layer to crystallize without having to undergo a separate high temperature annealing process after disposing the dielectric layer onto the conductive layer. Several examples of this method are expected to be very useful for forming dielectric layers with high dielectric constants because they avoid using a separate high temperature annealing process.
Abstract translation: 用于微电子器件的电气部件和用于形成电气部件的方法。 这种方法的一个具体实施方案包括将下面的层沉积到工件上，并在下层上形成导电层。 该方法可以通过在导电层上设置介电层来继续。 底层是导致电介质层具有比没有底层存在于导电层下方更高的介电常数的材料。 例如，下层可以赋予薄膜叠层的结构或另一性能，导致另外的非晶介质层结晶，而不必在将介电层设置在导电层上之后进行单独的高温退火工艺。 预期该方法的几个实例对于形成具有高介电常数的介电层非常有用，因为它们避免使用单独的高温退火工艺。
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2.发明申请
公开(公告)号：US20070264838A1
公开(公告)日：2007-11-15
申请号：US11431958
申请日：2006-05-10
Applicant: Rishikesh Krishnan , Dan Gealy , Vidya Srividya , Noel Rocklein
Inventor： Rishikesh Krishnan , Dan Gealy , Vidya Srividya , Noel Rocklein
IPC: H01L21/31 , H01L21/469
CPC classification number: H01G4/255 , H01L27/10852 , H01L28/65
Abstract: Electrical components for microelectronic devices and methods for forming electrical components. One particular embodiment of such a method comprises depositing an underlying layer onto a workpiece, and forming a conductive layer on the underlying layer. The method can continue by disposing a dielectric layer on the conductive layer. The underlying layer is a material that causes the dielectric layer to have a higher dielectric constant than without the underlying layer being present under the conductive layer. For example, the underlying layer can impart a structure or another property to the film stack that causes an otherwise amorphous dielectric layer to crystallize without having to undergo a separate high temperature annealing process after disposing the dielectric layer onto the conductive layer. Several examples of this method are expected to be very useful for forming dielectric layers with high dielectric constants because they avoid using a separate high temperature annealing process.
Abstract translation: 用于微电子器件的电气部件和用于形成电气部件的方法。 这种方法的一个具体实施方案包括将下面的层沉积到工件上，并在下层上形成导电层。 该方法可以通过在导电层上设置介电层来继续。 底层是导致电介质层具有比没有底层存在于导电层下方更高的介电常数的材料。 例如，下层可以赋予薄膜叠层的结构或另一性能，导致另外的非晶介质层结晶，而不必在将介质层设置在导电层上之后进行单独的高温退火工艺。 预期该方法的几个实例对于形成具有高介电常数的介电层非常有用，因为它们避免使用单独的高温退火工艺。
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公开(公告)号：US07968969B2
公开(公告)日：2011-06-28
申请号：US12502630
申请日：2009-07-14
Applicant: Rishikesh Krishnan , Dan Gealy , Vidya Srividya , Noel Rocklein
Inventor： Rishikesh Krishnan , Dan Gealy , Vidya Srividya , Noel Rocklein
IPC: H01L21/02
CPC classification number: H01G4/255 , H01L27/10852 , H01L28/65
Abstract: Electrical components for microelectronic devices and methods for forming electrical components. One particular embodiment of such a method comprises depositing an underlying layer onto a workpiece, and forming a conductive layer on the underlying layer. The method can continue by disposing a dielectric layer on the conductive layer. The underlying layer is a material that causes the dielectric layer to have a higher dielectric constant than without the underlying layer being present under the conductive layer. For example, the underlying layer can impart a structure or another property to the film stack that causes an otherwise amorphous dielectric layer to crystallize without having to undergo a separate high temperature annealing process after disposing the dielectric layer onto the conductive layer. Several examples of this method are expected to be very useful for forming dielectric layers with high dielectric constants because they avoid using a separate high temperature annealing process.
Abstract translation: 用于微电子器件的电气部件和用于形成电气部件的方法。 这种方法的一个具体实施方案包括将下面的层沉积到工件上，并在下层上形成导电层。 该方法可以通过在导电层上设置介电层来继续。 底层是导致电介质层具有比没有底层存在于导电层下方更高的介电常数的材料。 例如，下层可以赋予薄膜叠层的结构或另一性质，导致另外的无定形介电层结晶，而不必在将介电层设置在导电层上之后进行单独的高温退火工艺。 预期该方法的几个实例对于形成具有高介电常数的介电层非常有用，因为它们避免使用单独的高温退火工艺。
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4.发明申请
公开(公告)号：US20090273058A1
公开(公告)日：2009-11-05
申请号：US12502630
申请日：2009-07-14
Applicant: Rishikesh Krishnan , Dan Gealy , Vidya Srividya , Noel Rocklein
Inventor： Rishikesh Krishnan , Dan Gealy , Vidya Srividya , Noel Rocklein
CPC classification number: H01G4/255 , H01L27/10852 , H01L28/65
Abstract: Electrical components for microelectronic devices and methods for forming electrical components. One particular embodiment of such a method comprises depositing an underlying layer onto a workpiece, and forming a conductive layer on the underlying layer. The method can continue by disposing a dielectric layer on the conductive layer. The underlying layer is a material that causes the dielectric layer to have a higher dielectric constant than without the underlying layer being present under the conductive layer. For example, the underlying layer can impart a structure or another property to the film stack that causes an otherwise amorphous dielectric layer to crystallize without having to undergo a separate high temperature annealing process after disposing the dielectric layer onto the conductive layer. Several examples of this method are expected to be very useful for forming dielectric layers with high dielectric constants because they avoid using a separate high temperature annealing process.
Abstract translation: 用于微电子器件的电气部件和用于形成电气部件的方法。 这种方法的一个具体实施方案包括将下面的层沉积到工件上，并在下层上形成导电层。 该方法可以通过在导电层上设置介电层来继续。 底层是导致电介质层具有比没有底层存在于导电层下方更高的介电常数的材料。 例如，下层可以赋予薄膜叠层的结构或另一性质，导致另外的无定形介电层结晶，而不必在将介电层设置在导电层上之后进行单独的高温退火工艺。 预期该方法的几个实例对于形成具有高介电常数的介电层非常有用，因为它们避免使用单独的高温退火工艺。
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5.发明授权
公开(公告)号：US07560392B2
公开(公告)日：2009-07-14
申请号：US11431958
申请日：2006-05-10
Applicant: Rishikesh Krishnan , Dan Gealy , Vidya Srividya , Noel Rocklein
Inventor： Rishikesh Krishnan , Dan Gealy , Vidya Srividya , Noel Rocklein
IPC: H01L21/31 , H01L21/469
CPC classification number: H01G4/255 , H01L27/10852 , H01L28/65
Abstract: Electrical components for microelectronic devices and methods for forming electrical components. One particular embodiment of such a method comprises depositing an underlying layer onto a workpiece, and forming a conductive layer on the underlying layer. The method can continue by disposing a dielectric layer on the conductive layer. The underlying layer is a material that causes the dielectric layer to have a higher dielectric constant than without the underlying layer being present under the conductive layer. For example, the underlying layer can impart a structure or another property to the film stack that causes an otherwise amorphous dielectric layer to crystallize without having to undergo a separate high temperature annealing process after disposing the dielectric layer onto the conductive layer. Several examples of this method are expected to be very useful for forming dielectric layers with high dielectric constants because they avoid using a separate high temperature annealing process.
Abstract translation: 用于微电子器件的电气部件和用于形成电气部件的方法。 这种方法的一个具体实施方案包括将下面的层沉积到工件上，并在下层上形成导电层。 该方法可以通过在导电层上设置介电层来继续。 底层是导致电介质层具有比没有底层存在于导电层下方更高的介电常数的材料。 例如，下层可以赋予薄膜叠层的结构或另一性质，导致另外的无定形介电层结晶，而不必在将介电层设置在导电层上之后进行单独的高温退火工艺。 预期该方法的几个实例对于形成具有高介电常数的介电层非常有用，因为它们避免使用单独的高温退火工艺。
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公开(公告)号：US20090155486A1
公开(公告)日：2009-06-18
申请号：US11958952
申请日：2007-12-18
Applicant: Vishwanath Bhat , Rishikesh Krishnan , Dan Gealy
Inventor： Vishwanath Bhat , Rishikesh Krishnan , Dan Gealy
CPC classification number: C23C16/405 , C30B25/02 , C30B29/16 , H01G4/33 , H01G9/0032 , H01L28/65
Abstract: There is disclosed a method of forming crystalline tantalum pentoxide on a ruthenium-containing material having an oxygen-containing surface wherein the oxygen-containing surface is contacted with a treating composition, such as water, to remove at least some oxygen. Crystalline tantalum pentoxide is formed on at least a portion of the surface having reduced oxygen content.
Abstract translation: 公开了在具有含氧表面的含钌材料上形成结晶五氧化钽的方法，其中含氧表面与处理组合物如水接触以除去至少一些氧。 在具有降低的氧含量的表面的至少一部分上形成五氧化二钽结晶。
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公开(公告)号：US08012532B2
公开(公告)日：2011-09-06
申请号：US11958952
申请日：2007-12-18
Applicant: Vishwanath Bhat , Rishikesh Krishnan , Dan Gealy
Inventor： Vishwanath Bhat , Rishikesh Krishnan , Dan Gealy
CPC classification number: C23C16/405 , C30B25/02 , C30B29/16 , H01G4/33 , H01G9/0032 , H01L28/65
Abstract: There is disclosed a method of forming crystalline tantalum pentoxide on a ruthenium-containing material having an oxygen-containing surface wherein the oxygen-containing surface is contacted with a treating composition, such as water, to remove at least some oxygen. Crystalline tantalum pentoxide is formed on at least a portion of the surface having reduced oxygen content.
Abstract translation: 公开了在具有含氧表面的含钌材料上形成结晶五氧化钽的方法，其中含氧表面与处理组合物如水接触以除去至少一些氧。 在具有降低的氧含量的表面的至少一部分上形成五氧化二钽结晶。
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公开(公告)号：US08951903B2
公开(公告)日：2015-02-10
申请号：US13366025
申请日：2012-02-03
Applicant: Dan Gealy , Vishwanath Bhat , Cancheepuram V. Srividya , M. Noel Rocklein
Inventor： Dan Gealy , Vishwanath Bhat , Cancheepuram V. Srividya , M. Noel Rocklein
IPC: H01L21/3205 , H01L21/31 , H01L21/28 , C23C16/455 , H01L21/314 , H01L21/316 , H01L29/51 , H01L49/02 , H01L29/78
CPC classification number: H01L21/022 , C23C16/45529 , H01L21/02148 , H01L21/02194 , H01L21/0228 , H01L21/28194 , H01L21/3141 , H01L21/3142 , H01L21/31641 , H01L21/31645 , H01L28/40 , H01L28/56 , H01L29/517 , H01L29/78
Abstract: Graded dielectric layers and methods of fabricating such dielectric layers provide dielectrics in a variety of electronic structures for use in a wide range of electronic devices and systems. In an embodiment, a dielectric layer is graded with respect to a doping profile across the dielectric layer. In an embodiment, a dielectric layer is graded with respect to a crystalline structure profile across the dielectric layer. In an embodiment, a dielectric layer is formed by atomic layer deposition incorporating sequencing techniques to generate a doped dielectric material.
Abstract translation: 梯度介电层和制造这种电介质层的方法在各种电子结构中提供电介质以用于广泛的电子设备和系统。 在一个实施例中，电介质层相对于跨介电层的掺杂分布而分级。 在一个实施例中，电介质层相对于介电层上的晶体结构分布呈梯度分布。 在一个实施例中，通过包含测序技术的原子层沉积形成电介质层以产生掺杂的电介质材料。
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公开(公告)号：US20120202358A1
公开(公告)日：2012-08-09
申请号：US13366025
申请日：2012-02-03
Applicant: Dan Gealy , Vishwanath Bhat , Cancheepuram V. Srividya , M. Noel Rocklein
Inventor： Dan Gealy , Vishwanath Bhat , Cancheepuram V. Srividya , M. Noel Rocklein
IPC: H01L21/314
CPC classification number: H01L21/022 , C23C16/45529 , H01L21/02148 , H01L21/02194 , H01L21/0228 , H01L21/28194 , H01L21/3141 , H01L21/3142 , H01L21/31641 , H01L21/31645 , H01L28/40 , H01L28/56 , H01L29/517 , H01L29/78
Abstract: Graded dielectric layers and methods of fabricating such dielectric layers provide dielectrics in a variety of electronic structures for use in a wide range of electronic devices and systems. In an embodiment, a dielectric layer is graded with respect to a doping profile across the dielectric layer. In an embodiment, a dielectric layer is graded with respect to a crystalline structure profile across the dielectric layer. In an embodiment, a dielectric layer is formed by atomic layer deposition incorporating sequencing techniques to generate a doped dielectric material.
Abstract translation: 梯度介电层和制造这种电介质层的方法在各种电子结构中提供电介质以用于广泛的电子设备和系统。 在一个实施例中，电介质层相对于跨介电层的掺杂分布而分级。 在一个实施例中，电介质层相对于介电层上的晶体结构分布呈梯度分布。 在一个实施例中，通过包含测序技术的原子层沉积形成电介质层以产生掺杂的电介质材料。
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公开(公告)号：US08110469B2
公开(公告)日：2012-02-07
申请号：US11216542
申请日：2005-08-30
Applicant: Dan Gealy , Vishwanath Bhat , Cancheepuram V. Srividya , M. Noel Rocklein
Inventor： Dan Gealy , Vishwanath Bhat , Cancheepuram V. Srividya , M. Noel Rocklein
IPC: H01L21/336 , H01L21/3205 , H01L21/31 , H01L21/469
CPC classification number: H01L21/022 , C23C16/45529 , H01L21/02148 , H01L21/02194 , H01L21/0228 , H01L21/28194 , H01L21/3141 , H01L21/3142 , H01L21/31641 , H01L21/31645 , H01L28/40 , H01L28/56 , H01L29/517 , H01L29/78
Abstract: Graded dielectric layers and methods of fabricating such dielectric layers provide dielectrics in a variety of electronic structures for use in a wide range of electronic devices and systems. In an embodiment, a dielectric layer is graded with respect to a doping profile across the dielectric layer. In an embodiment, a dielectric layer is graded with respect to a crystalline structure profile across the dielectric layer. In an embodiment, a dielectric layer is formed by atomic layer deposition incorporating sequencing techniques to generate a doped dielectric material.
Abstract translation: 梯度介电层和制造这种电介质层的方法在各种电子结构中提供电介质以用于广泛的电子设备和系统。 在一个实施例中，电介质层相对于跨介电层的掺杂分布而分级。 在一个实施例中，电介质层相对于介电层上的晶体结构分布呈梯度分布。 在一个实施例中，通过包含测序技术的原子层沉积形成电介质层以产生掺杂的电介质材料。
