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    In situ formation of protective layer on silsesquioxane dielectric for dual damascene process
    1.
    发明授权
    In situ formation of protective layer on silsesquioxane dielectric for dual damascene process 有权
    在双镶嵌工艺中在倍半硅氧烷电介质上原位形成保护层

    公开(公告)号：US06348736B1

    公开(公告)日：2002-02-19

    申请号：US09429257

    申请日：1999-10-29

    申请人： Vincent J. McGahay ,  John P. Hummel ,  Joyce Liu ,  Rebecca Mih ,  Kamalesh Srivastava ,  Robert Cook ,  Stephen E. Greco

    发明人： Vincent J. McGahay ,  John P. Hummel ,  Joyce Liu ,  Rebecca Mih ,  Kamalesh Srivastava ,  Robert Cook ,  Stephen E. Greco

    IPC分类号： H01L2348

    CPC分类号： H01L21/76831 ,  H01L21/02134 ,  H01L21/02137 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/31144 ,  H01L21/3122 ,  H01L21/3124 ,  H01L21/76807

    摘要： Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. A first protective layer is formed in situ on the dielectric material, such as by exposing the material to an oxygen-containing or flourine containing plasma. Also, by performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. The first protective layer and the surface protective covering can be formed by essentially identical processes. A dual Damascene process for forming robust connections and vias to the chip can thus be made compatible with advanced dielectrics having particularly low dielectric constants to minimize conductor capacitance and support fast signal propagation and noise immunity even where conductors are closely spaced to each other.

    摘要翻译： 抗蚀剂显影剂可以攻击一些先进的介电材料，例如可以用作集成电路芯片的表面和形成在介电材料表面上的布线层之间的绝缘体的倍半硅氧烷材料。 在电介质材料上原位形成第一保护层，例如通过将材料暴露于含氧或含氟的等离子体中。 此外，通过进行抗蚀剂剥离或蚀刻工艺，其中将反应物材料从电介质材料外部供应或从电介质材料释放出来，可以形成非常薄的中间材料的表面保护覆盖层，其不能抵抗显影剂或多个 可能损坏可流动的氧化物材料的其他材料。 第一保护层和表面保护层可以通过基本相同的方法形成。 因此，与芯片形成牢固的连接和通孔的双镶嵌工艺可以与具有特别低介电常数的先进电介质相兼容，以最小化导体电容并支持快速的信号传播和抗噪声性，即使导体彼此间隔紧密。

    Interim oxidation of silsesquioxane dielectric for dual damascene process
    2.
    发明授权
    Interim oxidation of silsesquioxane dielectric for dual damascene process 有权
    双重镶嵌工艺的倍半硅氧烷电介质的中间氧化

    公开(公告)号：US06479884B2

    公开(公告)日：2002-11-12

    申请号：US09893786

    申请日：2001-06-29

    申请人： Robert Cook ,  Stephen E. Greco ,  John P. Hummel ,  Joyce Liu ,  Vincent J. McGahay ,  Rebecca Mih ,  Kamalesh Srivastava

    发明人： Robert Cook ,  Stephen E. Greco ,  John P. Hummel ,  Joyce Liu ,  Vincent J. McGahay ,  Rebecca Mih ,  Kamalesh Srivastava

    IPC分类号： H01L2358

    CPC分类号： H01L21/76808 ,  H01L2221/1063

    摘要： Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. By performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. A dual Damascene process for forming robust connections and vias to the chip can thus be made compatible with advanced dielectrics having particularly low dielectric constants to minimize conductor capacitance and support fast signal propagation and noise immunity even where conductors are closely spaced to each other.

    摘要翻译： 抗蚀剂显影剂可以攻击一些先进的介电材料，例如可以用作集成电路芯片的表面和形成在介电材料表面上的布线层之间的绝缘体的倍半硅氧烷材料。 通过进行抗蚀剂剥离或蚀刻工艺，其中将反应物材料从电介质材料外部供应或释放出来，可以形成非常薄的中间材料的表面保护覆盖层，其不能抵抗显影剂或多种其它材料 这可能会损坏可流动的氧化物材料。 因此，与芯片形成牢固的连接和通孔的双镶嵌工艺可以与具有特别低介电常数的先进电介质相兼容，以最小化导体电容并支持快速的信号传播和抗噪声性，即使导体彼此间隔紧密。

    Rendering optimization method and system
    10.
    发明申请
    Rendering optimization method and system 有权
    渲染优化方法和系统

    公开(公告)号：US20070168939A1

    公开(公告)日：2007-07-19

    申请号：US11274034

    申请日：2005-11-15

    申请人： Raymond Clark ,  Robert Cook ,  Ning Ren ,  Martin Rivers

    发明人： Raymond Clark ,  Robert Cook ,  Ning Ren ,  Martin Rivers

    IPC分类号： G06F9/44

    CPC分类号： G06K9/36 ,  G06K15/102 ,  G06K15/1825 ,  G06K15/1849 ,  H04N1/3872

    摘要： A method includes receiving a plurality of objects included within a print job. A first object of the plurality of objects and a second object of the plurality of objects are processed to define a first overlapping region between the first and second objects. The first object is modified to remove the first overlapping region, thus generating a modified first object.

    摘要翻译： 一种方法包括接收包括在打印作业内的多个对象。 多个对象中的第一对象和多个对象的第二对象被处理以限定第一和第二对象之间的第一重叠区域。 修改第一个对象以去除第一重叠区域，从而生成修改的第一对象。